i.MX: move i.MX31 CCM object to register array
With this i.MX25 and i.MX31 will have closer implementations. Moreover all i.MX31 CCM registers are now present. Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Jean-Christophe DUBOIS
Peter Maydell
parent
ac0d9dbf33
commit
fea01f9604
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@ -29,77 +29,73 @@
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static char const *imx31_ccm_reg_name(uint32_t reg)
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{
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static char unknown[20];
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switch (reg) {
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case 0:
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case IMX31_CCM_CCMR_REG:
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return "CCMR";
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case 1:
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case IMX31_CCM_PDR0_REG:
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return "PDR0";
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case 2:
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case IMX31_CCM_PDR1_REG:
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return "PDR1";
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case 3:
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case IMX31_CCM_RCSR_REG:
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return "RCSR";
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case 4:
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case IMX31_CCM_MPCTL_REG:
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return "MPCTL";
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case 5:
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case IMX31_CCM_UPCTL_REG:
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return "UPCTL";
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case 6:
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case IMX31_CCM_SPCTL_REG:
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return "SPCTL";
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case 7:
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case IMX31_CCM_COSR_REG:
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return "COSR";
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case 8:
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case IMX31_CCM_CGR0_REG:
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return "CGR0";
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case 9:
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case IMX31_CCM_CGR1_REG:
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return "CGR1";
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case 10:
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case IMX31_CCM_CGR2_REG:
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return "CGR2";
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case 11:
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case IMX31_CCM_WIMR_REG:
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return "WIMR";
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case 12:
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case IMX31_CCM_LDC_REG:
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return "LDC";
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case 13:
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case IMX31_CCM_DCVR0_REG:
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return "DCVR0";
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case 14:
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case IMX31_CCM_DCVR1_REG:
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return "DCVR1";
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case 15:
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case IMX31_CCM_DCVR2_REG:
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return "DCVR2";
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case 16:
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case IMX31_CCM_DCVR3_REG:
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return "DCVR3";
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case 17:
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case IMX31_CCM_LTR0_REG:
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return "LTR0";
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case 18:
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case IMX31_CCM_LTR1_REG:
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return "LTR1";
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case 19:
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case IMX31_CCM_LTR2_REG:
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return "LTR2";
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case 20:
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case IMX31_CCM_LTR3_REG:
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return "LTR3";
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case 21:
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case IMX31_CCM_LTBR0_REG:
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return "LTBR0";
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case 22:
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case IMX31_CCM_LTBR1_REG:
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return "LTBR1";
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case 23:
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case IMX31_CCM_PMCR0_REG:
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return "PMCR0";
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case 24:
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case IMX31_CCM_PMCR1_REG:
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return "PMCR1";
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case 25:
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case IMX31_CCM_PDR2_REG:
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return "PDR2";
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default:
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return "???";
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sprintf(unknown, "[%d ?]", reg);
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return unknown;
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}
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}
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static const VMStateDescription vmstate_imx31_ccm = {
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.name = TYPE_IMX31_CCM,
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.version_id = 1,
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.minimum_version_id = 1,
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.version_id = 2,
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.minimum_version_id = 2,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(ccmr, IMX31CCMState),
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VMSTATE_UINT32(pdr0, IMX31CCMState),
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VMSTATE_UINT32(pdr1, IMX31CCMState),
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VMSTATE_UINT32(mpctl, IMX31CCMState),
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VMSTATE_UINT32(spctl, IMX31CCMState),
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VMSTATE_UINT32_ARRAY(cgr, IMX31CCMState, 3),
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VMSTATE_UINT32(pmcr0, IMX31CCMState),
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VMSTATE_UINT32(pmcr1, IMX31CCMState),
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VMSTATE_UINT32_ARRAY(reg, IMX31CCMState, IMX31_CCM_MAX_REG),
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VMSTATE_END_OF_LIST()
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},
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};
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@ -109,10 +105,10 @@ static uint32_t imx31_ccm_get_pll_ref_clk(IMXCCMState *dev)
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uint32_t freq = 0;
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IMX31CCMState *s = IMX31_CCM(dev);
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if ((s->ccmr & CCMR_PRCS) == 2) {
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if (s->ccmr & CCMR_FPME) {
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if ((s->reg[IMX31_CCM_CCMR_REG] & CCMR_PRCS) == 2) {
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if (s->reg[IMX31_CCM_CCMR_REG] & CCMR_FPME) {
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freq = CKIL_FREQ;
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if (s->ccmr & CCMR_FPMF) {
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if (s->reg[IMX31_CCM_CCMR_REG] & CCMR_FPMF) {
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freq *= 1024;
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}
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}
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@ -130,7 +126,8 @@ static uint32_t imx31_ccm_get_mpll_clk(IMXCCMState *dev)
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uint32_t freq;
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IMX31CCMState *s = IMX31_CCM(dev);
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freq = imx_ccm_calc_pll(s->mpctl, imx31_ccm_get_pll_ref_clk(dev));
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freq = imx_ccm_calc_pll(s->reg[IMX31_CCM_MPCTL_REG],
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imx31_ccm_get_pll_ref_clk(dev));
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DPRINTF("freq = %d\n", freq);
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@ -142,7 +139,8 @@ static uint32_t imx31_ccm_get_mcu_main_clk(IMXCCMState *dev)
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uint32_t freq;
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IMX31CCMState *s = IMX31_CCM(dev);
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if ((s->ccmr & CCMR_MDS) || !(s->ccmr & CCMR_MPE)) {
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if ((s->reg[IMX31_CCM_CCMR_REG] & CCMR_MDS) ||
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!(s->reg[IMX31_CCM_CCMR_REG] & CCMR_MPE)) {
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freq = imx31_ccm_get_pll_ref_clk(dev);
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} else {
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freq = imx31_ccm_get_mpll_clk(dev);
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@ -158,7 +156,8 @@ static uint32_t imx31_ccm_get_mcu_clk(IMXCCMState *dev)
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uint32_t freq;
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IMX31CCMState *s = IMX31_CCM(dev);
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freq = imx31_ccm_get_mcu_main_clk(dev) / (1 + EXTRACT(s->pdr0, MCU));
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freq = imx31_ccm_get_mcu_main_clk(dev)
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/ (1 + EXTRACT(s->reg[IMX31_CCM_PDR0_REG], MCU));
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DPRINTF("freq = %d\n", freq);
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@ -170,7 +169,8 @@ static uint32_t imx31_ccm_get_hsp_clk(IMXCCMState *dev)
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uint32_t freq;
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IMX31CCMState *s = IMX31_CCM(dev);
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freq = imx31_ccm_get_mcu_main_clk(dev) / (1 + EXTRACT(s->pdr0, HSP));
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freq = imx31_ccm_get_mcu_main_clk(dev)
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/ (1 + EXTRACT(s->reg[IMX31_CCM_PDR0_REG], HSP));
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DPRINTF("freq = %d\n", freq);
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@ -182,7 +182,8 @@ static uint32_t imx31_ccm_get_hclk_clk(IMXCCMState *dev)
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uint32_t freq;
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IMX31CCMState *s = IMX31_CCM(dev);
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freq = imx31_ccm_get_mcu_main_clk(dev) / (1 + EXTRACT(s->pdr0, MAX));
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freq = imx31_ccm_get_mcu_main_clk(dev)
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/ (1 + EXTRACT(s->reg[IMX31_CCM_PDR0_REG], MAX));
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DPRINTF("freq = %d\n", freq);
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@ -194,7 +195,8 @@ static uint32_t imx31_ccm_get_ipg_clk(IMXCCMState *dev)
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uint32_t freq;
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IMX31CCMState *s = IMX31_CCM(dev);
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freq = imx31_ccm_get_hclk_clk(dev) / (1 + EXTRACT(s->pdr0, IPG));
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freq = imx31_ccm_get_hclk_clk(dev)
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/ (1 + EXTRACT(s->reg[IMX31_CCM_PDR0_REG], IPG));
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DPRINTF("freq = %d\n", freq);
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@ -237,14 +239,24 @@ static void imx31_ccm_reset(DeviceState *dev)
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DPRINTF("()\n");
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s->ccmr = 0x074b0b7d;
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s->pdr0 = 0xff870b48;
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s->pdr1 = 0x49fcfe7f;
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s->mpctl = 0x04001800;
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s->cgr[0] = s->cgr[1] = s->cgr[2] = 0xffffffff;
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s->spctl = 0x04043001;
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s->pmcr0 = 0x80209828;
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s->pmcr1 = 0x00aa0000;
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memset(s->reg, 0, sizeof(uint32_t) * IMX31_CCM_MAX_REG);
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s->reg[IMX31_CCM_CCMR_REG] = 0x074b0b7d;
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s->reg[IMX31_CCM_PDR0_REG] = 0xff870b48;
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s->reg[IMX31_CCM_PDR1_REG] = 0x49fcfe7f;
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s->reg[IMX31_CCM_RCSR_REG] = 0x007f0000;
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s->reg[IMX31_CCM_MPCTL_REG] = 0x04001800;
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s->reg[IMX31_CCM_UPCTL_REG] = 0x04051c03;
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s->reg[IMX31_CCM_SPCTL_REG] = 0x04043001;
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s->reg[IMX31_CCM_COSR_REG] = 0x00000280;
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s->reg[IMX31_CCM_CGR0_REG] = 0xffffffff;
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s->reg[IMX31_CCM_CGR1_REG] = 0xffffffff;
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s->reg[IMX31_CCM_CGR2_REG] = 0xffffffff;
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s->reg[IMX31_CCM_WIMR_REG] = 0xffffffff;
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s->reg[IMX31_CCM_LTR1_REG] = 0x00004040;
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s->reg[IMX31_CCM_PMCR0_REG] = 0x80209828;
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s->reg[IMX31_CCM_PMCR1_REG] = 0x00aa0000;
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s->reg[IMX31_CCM_PDR2_REG] = 0x00000285;
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}
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static uint64_t imx31_ccm_read(void *opaque, hwaddr offset, unsigned size)
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@ -252,41 +264,11 @@ static uint64_t imx31_ccm_read(void *opaque, hwaddr offset, unsigned size)
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uint32 value = 0;
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IMX31CCMState *s = (IMX31CCMState *)opaque;
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switch (offset >> 2) {
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case 0: /* CCMR */
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value = s->ccmr;
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break;
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case 1:
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value = s->pdr0;
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break;
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case 2:
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value = s->pdr1;
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break;
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case 4:
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value = s->mpctl;
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break;
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case 6:
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value = s->spctl;
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break;
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case 8:
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value = s->cgr[0];
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break;
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case 9:
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value = s->cgr[1];
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break;
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case 10:
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value = s->cgr[2];
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break;
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case 18: /* LTR1 */
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value = 0x00004040;
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break;
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case 23:
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value = s->pmcr0;
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break;
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default:
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if ((offset >> 2) < IMX31_CCM_MAX_REG) {
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value = s->reg[offset >> 2];
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} else {
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qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
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HWADDR_PRIx "\n", TYPE_IMX31_CCM, __func__, offset);
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break;
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}
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DPRINTF("reg[%s] => 0x%" PRIx32 "\n", imx31_ccm_reg_name(offset >> 2),
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@ -304,29 +286,29 @@ static void imx31_ccm_write(void *opaque, hwaddr offset, uint64_t value,
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(uint32_t)value);
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switch (offset >> 2) {
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case 0:
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s->ccmr = CCMR_FPMF | (value & 0x3b6fdfff);
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case IMX31_CCM_CCMR_REG:
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s->reg[IMX31_CCM_CCMR_REG] = CCMR_FPMF | (value & 0x3b6fdfff);
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break;
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case 1:
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s->pdr0 = value & 0xff9f3fff;
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case IMX31_CCM_PDR0_REG:
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s->reg[IMX31_CCM_PDR0_REG] = value & 0xff9f3fff;
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break;
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case 2:
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s->pdr1 = value;
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case IMX31_CCM_PDR1_REG:
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s->reg[IMX31_CCM_PDR1_REG] = value;
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break;
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case 4:
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s->mpctl = value & 0xbfff3fff;
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case IMX31_CCM_MPCTL_REG:
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s->reg[IMX31_CCM_MPCTL_REG] = value & 0xbfff3fff;
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break;
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case 6:
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s->spctl = value & 0xbfff3fff;
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case IMX31_CCM_SPCTL_REG:
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s->reg[IMX31_CCM_SPCTL_REG] = value & 0xbfff3fff;
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break;
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case 8:
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s->cgr[0] = value;
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case IMX31_CCM_CGR0_REG:
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s->reg[IMX31_CCM_CGR0_REG] = value;
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break;
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case 9:
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s->cgr[1] = value;
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case IMX31_CCM_CGR1_REG:
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s->reg[IMX31_CCM_CGR1_REG] = value;
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break;
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case 10:
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s->cgr[2] = value;
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case IMX31_CCM_CGR2_REG:
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s->reg[IMX31_CCM_CGR2_REG] = value;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
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@ -13,6 +13,34 @@
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#include "hw/misc/imx_ccm.h"
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#define IMX31_CCM_CCMR_REG 0
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#define IMX31_CCM_PDR0_REG 1
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#define IMX31_CCM_PDR1_REG 2
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#define IMX31_CCM_RCSR_REG 3
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#define IMX31_CCM_MPCTL_REG 4
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#define IMX31_CCM_UPCTL_REG 5
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#define IMX31_CCM_SPCTL_REG 6
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#define IMX31_CCM_COSR_REG 7
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#define IMX31_CCM_CGR0_REG 8
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#define IMX31_CCM_CGR1_REG 9
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#define IMX31_CCM_CGR2_REG 10
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#define IMX31_CCM_WIMR_REG 11
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#define IMX31_CCM_LDC_REG 12
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#define IMX31_CCM_DCVR0_REG 13
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#define IMX31_CCM_DCVR1_REG 14
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#define IMX31_CCM_DCVR2_REG 15
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#define IMX31_CCM_DCVR3_REG 16
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#define IMX31_CCM_LTR0_REG 17
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#define IMX31_CCM_LTR1_REG 18
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#define IMX31_CCM_LTR2_REG 19
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#define IMX31_CCM_LTR3_REG 20
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#define IMX31_CCM_LTBR0_REG 21
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#define IMX31_CCM_LTBR1_REG 22
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#define IMX31_CCM_PMCR0_REG 23
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#define IMX31_CCM_PMCR1_REG 24
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#define IMX31_CCM_PDR2_REG 25
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#define IMX31_CCM_MAX_REG 26
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/* CCMR */
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#define CCMR_FPME (1<<0)
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#define CCMR_MPE (1<<3)
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@ -53,14 +81,8 @@ typedef struct IMX31CCMState {
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/* <public> */
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MemoryRegion iomem;
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uint32_t ccmr;
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uint32_t pdr0;
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uint32_t pdr1;
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uint32_t mpctl;
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uint32_t spctl;
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uint32_t cgr[3];
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uint32_t pmcr0;
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uint32_t pmcr1;
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uint32_t reg[IMX31_CCM_MAX_REG];
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} IMX31CCMState;
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#endif /* IMX31_CCM_H */
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