tcg-ppc64: Streamline tcg_out_tlb_read
Less conditional compilation. Merge an add insn with the indexed memory load insn. Load the tlb addend earlier. Avoid the address update memory form. Fix a bug in not allowing large enough tlb offsets for some guests. Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson
parent
fa94c3be7a
commit
fedee3e7fd
@ -31,13 +31,11 @@
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static uint8_t *tb_ret_addr;
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#define FAST_PATH
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#if TARGET_LONG_BITS == 32
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#define LD_ADDR LWZU
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#define LD_ADDR LWZ
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#define CMP_L 0
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#else
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#define LD_ADDR LDU
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#define LD_ADDR LD
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#define CMP_L (1<<21)
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#endif
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@ -816,38 +814,78 @@ static const void * const qemu_st_helpers[4] = {
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helper_stq_mmu,
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};
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static void tcg_out_tlb_read(TCGContext *s, TCGReg r0, TCGReg r1, TCGReg r2,
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TCGReg addr_reg, int s_bits, int offset)
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/* Perform the TLB load and compare. Places the result of the comparison
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in CR7, loads the addend of the TLB into R3, and returns the register
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containing the guest address (zero-extended into R4). Clobbers R0 and R2. */
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static TCGReg tcg_out_tlb_read(TCGContext *s, int s_bits, TCGReg addr_reg,
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int mem_index, bool is_read)
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{
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#if TARGET_LONG_BITS == 32
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tcg_out_ext32u(s, addr_reg, addr_reg);
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int cmp_off
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= (is_read
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? offsetof(CPUArchState, tlb_table[mem_index][0].addr_read)
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: offsetof(CPUArchState, tlb_table[mem_index][0].addr_write));
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int add_off = offsetof(CPUArchState, tlb_table[mem_index][0].addend);
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TCGReg base = TCG_AREG0;
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tcg_out_rlw(s, RLWINM, r0, addr_reg,
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32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
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32 - (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS),
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31 - CPU_TLB_ENTRY_BITS);
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tcg_out32(s, ADD | TAB(r0, r0, TCG_AREG0));
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tcg_out32(s, LWZU | TAI(r1, r0, offset));
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tcg_out_rlw(s, RLWINM, r2, addr_reg, 0,
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(32 - s_bits) & 31, 31 - TARGET_PAGE_BITS);
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#else
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tcg_out_rld(s, RLDICL, r0, addr_reg,
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64 - TARGET_PAGE_BITS,
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64 - CPU_TLB_BITS);
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tcg_out_shli64(s, r0, r0, CPU_TLB_ENTRY_BITS);
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tcg_out32(s, ADD | TAB(r0, r0, TCG_AREG0));
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tcg_out32(s, LD_ADDR | TAI(r1, r0, offset));
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if (!s_bits) {
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tcg_out_rld(s, RLDICR, r2, addr_reg, 0, 63 - TARGET_PAGE_BITS);
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/* Extract the page index, shifted into place for tlb index. */
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if (TARGET_LONG_BITS == 32) {
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/* Zero-extend the address into a place helpful for further use. */
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tcg_out_ext32u(s, TCG_REG_R4, addr_reg);
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addr_reg = TCG_REG_R4;
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} else {
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tcg_out_rld(s, RLDICL, r2, addr_reg,
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64 - TARGET_PAGE_BITS,
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TARGET_PAGE_BITS - s_bits);
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tcg_out_rld(s, RLDICL, r2, r2, TARGET_PAGE_BITS, 0);
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tcg_out_rld(s, RLDICL, TCG_REG_R3, addr_reg,
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64 - TARGET_PAGE_BITS, 64 - CPU_TLB_BITS);
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}
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#endif
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/* Compensate for very large offsets. */
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if (add_off >= 0x8000) {
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/* Most target env are smaller than 32k; none are larger than 64k.
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Simplify the logic here merely to offset by 0x7ff0, giving us a
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range just shy of 64k. Check this assumption. */
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QEMU_BUILD_BUG_ON(offsetof(CPUArchState,
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tlb_table[NB_MMU_MODES - 1][1])
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> 0x7ff0 + 0x7fff);
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tcg_out32(s, ADDI | TAI(TCG_REG_R2, base, 0x7ff0));
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base = TCG_REG_R2;
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cmp_off -= 0x7ff0;
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add_off -= 0x7ff0;
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}
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/* Extraction and shifting, part 2. */
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if (TARGET_LONG_BITS == 32) {
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tcg_out_rlw(s, RLWINM, TCG_REG_R3, addr_reg,
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32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
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32 - (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS),
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31 - CPU_TLB_ENTRY_BITS);
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} else {
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tcg_out_shli64(s, TCG_REG_R3, TCG_REG_R3, CPU_TLB_ENTRY_BITS);
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}
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tcg_out32(s, ADD | TAB(TCG_REG_R3, TCG_REG_R3, base));
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/* Load the tlb comparator. */
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tcg_out32(s, LD_ADDR | TAI(TCG_REG_R2, TCG_REG_R3, cmp_off));
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/* Load the TLB addend for use on the fast path. Do this asap
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to minimize any load use delay. */
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tcg_out32(s, LD | TAI(TCG_REG_R3, TCG_REG_R3, add_off));
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/* Clear the non-page, non-alignment bits from the address. */
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if (TARGET_LONG_BITS == 32) {
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tcg_out_rlw(s, RLWINM, TCG_REG_R0, addr_reg, 0,
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(32 - s_bits) & 31, 31 - TARGET_PAGE_BITS);
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} else if (!s_bits) {
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tcg_out_rld(s, RLDICR, TCG_REG_R0, addr_reg, 0, 63 - TARGET_PAGE_BITS);
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} else {
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tcg_out_rld(s, RLDICL, TCG_REG_R0, addr_reg,
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64 - TARGET_PAGE_BITS, TARGET_PAGE_BITS - s_bits);
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tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, TARGET_PAGE_BITS, 0);
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}
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tcg_out32(s, CMP | BF(7) | RA(TCG_REG_R0) | RB(TCG_REG_R2) | CMP_L);
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return addr_reg;
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}
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#endif
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@ -875,10 +913,10 @@ static const uint32_t qemu_exts_opc[4] = {
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static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
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{
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TCGReg addr_reg, data_reg, r0, r1, rbase;
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TCGReg addr_reg, data_reg, rbase;
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uint32_t insn, s_bits;
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#ifdef CONFIG_SOFTMMU
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TCGReg r2, ir;
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TCGReg ir;
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int mem_index;
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void *label1_ptr, *label2_ptr;
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#endif
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@ -890,20 +928,10 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
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#ifdef CONFIG_SOFTMMU
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mem_index = *args;
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r0 = TCG_REG_R3;
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r1 = TCG_REG_R4;
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r2 = TCG_REG_R0;
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rbase = 0;
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tcg_out_tlb_read(s, r0, r1, r2, addr_reg, s_bits,
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offsetof(CPUArchState, tlb_table[mem_index][0].addr_read));
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tcg_out32(s, CMP | BF(7) | RA(r2) | RB(r1) | CMP_L);
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addr_reg = tcg_out_tlb_read(s, s_bits, addr_reg, mem_index, true);
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label1_ptr = s->code_ptr;
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#ifdef FAST_PATH
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tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_TRUE);
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#endif
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/* slow path */
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ir = TCG_REG_R3;
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@ -919,42 +947,33 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
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} else if (data_reg != TCG_REG_R3) {
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tcg_out_mov(s, TCG_TYPE_I64, data_reg, TCG_REG_R3);
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}
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label2_ptr = s->code_ptr;
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tcg_out32(s, B);
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/* label1: fast path */
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#ifdef FAST_PATH
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reloc_pc14(label1_ptr, (tcg_target_long)s->code_ptr);
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#endif
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/* r0 now contains &env->tlb_table[mem_index][index].addr_read */
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tcg_out32(s, LD | TAI(r0, r0,
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offsetof(CPUTLBEntry, addend)
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- offsetof(CPUTLBEntry, addr_read)));
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/* r0 = env->tlb_table[mem_index][index].addend */
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tcg_out32(s, ADD | TAB(r0, r0, addr_reg));
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/* r0 = env->tlb_table[mem_index][index].addend + addr */
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rbase = TCG_REG_R3;
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#else /* !CONFIG_SOFTMMU */
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#if TARGET_LONG_BITS == 32
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tcg_out_ext32u(s, addr_reg, addr_reg);
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#endif
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r0 = addr_reg;
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r1 = TCG_REG_R3;
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rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
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if (TARGET_LONG_BITS == 32) {
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tcg_out_ext32u(s, TCG_REG_R2, addr_reg);
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addr_reg = TCG_REG_R2;
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}
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#endif
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insn = qemu_ldx_opc[opc];
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if (!HAVE_ISA_2_06 && insn == LDBRX) {
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tcg_out32(s, ADDI | TAI(r1, r0, 4));
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tcg_out32(s, LWBRX | TAB(data_reg, rbase, r0));
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tcg_out32(s, LWBRX | TAB( r1, rbase, r1));
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tcg_out_rld(s, RLDIMI, data_reg, r1, 32, 0);
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tcg_out32(s, ADDI | TAI(TCG_REG_R0, addr_reg, 4));
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tcg_out32(s, LWBRX | TAB(data_reg, rbase, addr_reg));
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tcg_out32(s, LWBRX | TAB(TCG_REG_R0, rbase, TCG_REG_R0));
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tcg_out_rld(s, RLDIMI, data_reg, TCG_REG_R0, 32, 0);
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} else if (insn) {
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tcg_out32(s, insn | TAB(data_reg, rbase, r0));
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tcg_out32(s, insn | TAB(data_reg, rbase, addr_reg));
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} else {
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insn = qemu_ldx_opc[s_bits];
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tcg_out32(s, insn | TAB(data_reg, rbase, r0));
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tcg_out32(s, insn | TAB(data_reg, rbase, addr_reg));
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insn = qemu_exts_opc[s_bits];
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tcg_out32(s, insn | RA(data_reg) | RS(data_reg));
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}
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@ -966,10 +985,10 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc)
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static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
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{
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TCGReg addr_reg, r0, r1, rbase, data_reg;
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TCGReg addr_reg, rbase, data_reg;
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uint32_t insn;
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#ifdef CONFIG_SOFTMMU
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TCGReg r2, ir;
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TCGReg ir;
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int mem_index;
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void *label1_ptr, *label2_ptr;
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#endif
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@ -980,20 +999,10 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
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#ifdef CONFIG_SOFTMMU
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mem_index = *args;
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r0 = TCG_REG_R3;
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r1 = TCG_REG_R4;
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r2 = TCG_REG_R0;
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rbase = 0;
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tcg_out_tlb_read(s, r0, r1, r2, addr_reg, opc,
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offsetof(CPUArchState, tlb_table[mem_index][0].addr_write));
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tcg_out32(s, CMP | BF(7) | RA(r2) | RB(r1) | CMP_L);
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addr_reg = tcg_out_tlb_read(s, opc, addr_reg, mem_index, false);
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label1_ptr = s->code_ptr;
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#ifdef FAST_PATH
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tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_TRUE);
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#endif
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/* slow path */
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ir = TCG_REG_R3;
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@ -1008,34 +1017,25 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc)
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tcg_out32(s, B);
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/* label1: fast path */
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#ifdef FAST_PATH
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reloc_pc14(label1_ptr, (tcg_target_long)s->code_ptr);
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#endif
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tcg_out32(s, LD | TAI(r0, r0,
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offsetof(CPUTLBEntry, addend)
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- offsetof(CPUTLBEntry, addr_write)));
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/* r0 = env->tlb_table[mem_index][index].addend */
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tcg_out32(s, ADD | TAB(r0, r0, addr_reg));
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/* r0 = env->tlb_table[mem_index][index].addend + addr */
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reloc_pc14(label1_ptr, (tcg_target_long) s->code_ptr);
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rbase = TCG_REG_R3;
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#else /* !CONFIG_SOFTMMU */
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#if TARGET_LONG_BITS == 32
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tcg_out_ext32u(s, addr_reg, addr_reg);
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#endif
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r1 = TCG_REG_R3;
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r0 = addr_reg;
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rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
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if (TARGET_LONG_BITS == 32) {
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tcg_out_ext32u(s, TCG_REG_R2, addr_reg);
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addr_reg = TCG_REG_R2;
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}
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#endif
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insn = qemu_stx_opc[opc];
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if (!HAVE_ISA_2_06 && insn == STDBRX) {
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tcg_out32(s, STWBRX | SAB(data_reg, rbase, r0));
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tcg_out32(s, ADDI | TAI(r1, r0, 4));
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tcg_out32(s, STWBRX | SAB(data_reg, rbase, addr_reg));
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tcg_out32(s, ADDI | TAI(TCG_REG_R2, addr_reg, 4));
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tcg_out_shri64(s, TCG_REG_R0, data_reg, 32);
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tcg_out32(s, STWBRX | SAB(TCG_REG_R0, rbase, r1));
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tcg_out32(s, STWBRX | SAB(TCG_REG_R0, rbase, TCG_REG_R2));
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} else {
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tcg_out32(s, insn | SAB(data_reg, rbase, r0));
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tcg_out32(s, insn | SAB(data_reg, rbase, addr_reg));
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}
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#ifdef CONFIG_SOFTMMU
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