target/xtensa updates:
- instantiate local memories in xtensa sim machine; - add two missing include files to xtensa core importing script. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJYveONAAoJEFH5zJH4P6BETpwP/Rs4GJWQwfThSRCkfKRG3H8n Iy71u0i8Hf4dBmHmn10X8tl+VWe6NEF3HjcZR0lrnC8dj6ZkGXuxd2nd3SuMFwhp IV7iWOeKi3uGQMGxRgkFSuSY+KggH3ppcERc+mR1HOgMWQM/HJ/ijtPHIgveskFW M/PT+x0fMYN3pPNrHrOS98oDbiN2D6WG+t7Go+J/K5fx5z98hGq1lYHUq02XFnvu RPFhGhx5ni3Ps7rp6YPXGUL0Q+jCqDfbiDwbX4wl9cgDcWtjdBA/8r/cLjd327RY aBZ/9QQSTisp5ky4GuskFX0l7XWH7py0opP5NiL6eolFaUdnaeTdP4IKXLeLM4Z3 fD4mFISGF+kAzfDGPnrPcWxgx0UuON8EQ2Z32grvRhEiFrqER+4fjPkStWHj+vVR D1mLEDwq4pjMuEou6qwm5C5rFlOWHhX/1H1vrfEsJbH6h30xdqJBRYwblTbLcjcJ 1KY3kx6WiyqZZ+7PIHYoGspEsUYgnqZhBa65WsRtSjvyjOkIYom2MSkVasg39VCD Q+nZIUh/IeUrwVfHTtTAwoDPhUclR7wNY//8w+e25b7V7Ed/UWfqj9I2LMg+XYPZ cU11P85HKpUNFczMIy809DaoBCB6pstRxS/GuPlM1e5NAABJJ0NzcUynM7qw3f+R JQH8SssTKxsEG08OOHMT =NOaN -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/xtensa/tags/20170306-xtensa' into staging target/xtensa updates: - instantiate local memories in xtensa sim machine; - add two missing include files to xtensa core importing script. # gpg: Signature made Mon 06 Mar 2017 22:32:45 GMT # gpg: using RSA key 0x51F9CC91F83FA044 # gpg: Good signature from "Max Filippov <filippov@cadence.com>" # gpg: aka "Max Filippov <max.filippov@cogentembedded.com>" # gpg: aka "Max Filippov <jcmvbkbc@gmail.com>" # Primary key fingerprint: 2B67 854B 98E5 327D CDEB 17D8 51F9 CC91 F83F A044 * remotes/xtensa/tags/20170306-xtensa: target/xtensa: add two missing headers to core import script target/xtensa: sim: instantiate local memories Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
ff79d5e939
|
@ -37,6 +37,27 @@
|
||||||
#include "exec/address-spaces.h"
|
#include "exec/address-spaces.h"
|
||||||
#include "qemu/error-report.h"
|
#include "qemu/error-report.h"
|
||||||
|
|
||||||
|
static void xtensa_create_memory_regions(const XtensaMemory *memory,
|
||||||
|
const char *name)
|
||||||
|
{
|
||||||
|
unsigned i;
|
||||||
|
char *num_name = malloc(strlen(name) + sizeof(i) * 3 + 1);
|
||||||
|
|
||||||
|
for (i = 0; i < memory->num; ++i) {
|
||||||
|
MemoryRegion *m;
|
||||||
|
|
||||||
|
sprintf(num_name, "%s%u", name, i);
|
||||||
|
m = g_malloc(sizeof(*m));
|
||||||
|
memory_region_init_ram(m, NULL, num_name,
|
||||||
|
memory->location[i].size,
|
||||||
|
&error_fatal);
|
||||||
|
vmstate_register_ram_global(m);
|
||||||
|
memory_region_add_subregion(get_system_memory(),
|
||||||
|
memory->location[i].addr, m);
|
||||||
|
}
|
||||||
|
free(num_name);
|
||||||
|
}
|
||||||
|
|
||||||
static uint64_t translate_phys_addr(void *opaque, uint64_t addr)
|
static uint64_t translate_phys_addr(void *opaque, uint64_t addr)
|
||||||
{
|
{
|
||||||
XtensaCPU *cpu = opaque;
|
XtensaCPU *cpu = opaque;
|
||||||
|
@ -55,7 +76,6 @@ static void xtensa_sim_init(MachineState *machine)
|
||||||
{
|
{
|
||||||
XtensaCPU *cpu = NULL;
|
XtensaCPU *cpu = NULL;
|
||||||
CPUXtensaState *env = NULL;
|
CPUXtensaState *env = NULL;
|
||||||
MemoryRegion *ram, *rom;
|
|
||||||
ram_addr_t ram_size = machine->ram_size;
|
ram_addr_t ram_size = machine->ram_size;
|
||||||
const char *cpu_model = machine->cpu_model;
|
const char *cpu_model = machine->cpu_model;
|
||||||
const char *kernel_filename = machine->kernel_filename;
|
const char *kernel_filename = machine->kernel_filename;
|
||||||
|
@ -82,15 +102,17 @@ static void xtensa_sim_init(MachineState *machine)
|
||||||
sim_reset(cpu);
|
sim_reset(cpu);
|
||||||
}
|
}
|
||||||
|
|
||||||
ram = g_malloc(sizeof(*ram));
|
if (env) {
|
||||||
memory_region_init_ram(ram, NULL, "xtensa.sram", ram_size, &error_fatal);
|
XtensaMemory sysram = env->config->sysram;
|
||||||
vmstate_register_ram_global(ram);
|
|
||||||
memory_region_add_subregion(get_system_memory(), 0, ram);
|
|
||||||
|
|
||||||
rom = g_malloc(sizeof(*rom));
|
sysram.location[0].size = ram_size;
|
||||||
memory_region_init_ram(rom, NULL, "xtensa.rom", 0x1000, &error_fatal);
|
xtensa_create_memory_regions(&env->config->instrom, "xtensa.instrom");
|
||||||
vmstate_register_ram_global(rom);
|
xtensa_create_memory_regions(&env->config->instram, "xtensa.instram");
|
||||||
memory_region_add_subregion(get_system_memory(), 0xfe000000, rom);
|
xtensa_create_memory_regions(&env->config->datarom, "xtensa.datarom");
|
||||||
|
xtensa_create_memory_regions(&env->config->dataram, "xtensa.dataram");
|
||||||
|
xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom");
|
||||||
|
xtensa_create_memory_regions(&sysram, "xtensa.sysram");
|
||||||
|
}
|
||||||
|
|
||||||
if (kernel_filename) {
|
if (kernel_filename) {
|
||||||
uint64_t elf_entry;
|
uint64_t elf_entry;
|
||||||
|
|
|
@ -212,6 +212,7 @@ enum {
|
||||||
#define MAX_NCCOMPARE 3
|
#define MAX_NCCOMPARE 3
|
||||||
#define MAX_TLB_WAY_SIZE 8
|
#define MAX_TLB_WAY_SIZE 8
|
||||||
#define MAX_NDBREAK 2
|
#define MAX_NDBREAK 2
|
||||||
|
#define MAX_NMEMORY 4
|
||||||
|
|
||||||
#define REGION_PAGE_MASK 0xe0000000
|
#define REGION_PAGE_MASK 0xe0000000
|
||||||
|
|
||||||
|
@ -321,6 +322,14 @@ typedef struct XtensaCcompareTimer {
|
||||||
QEMUTimer *timer;
|
QEMUTimer *timer;
|
||||||
} XtensaCcompareTimer;
|
} XtensaCcompareTimer;
|
||||||
|
|
||||||
|
typedef struct XtensaMemory {
|
||||||
|
unsigned num;
|
||||||
|
struct XtensaMemoryRegion {
|
||||||
|
uint32_t addr;
|
||||||
|
uint32_t size;
|
||||||
|
} location[MAX_NMEMORY];
|
||||||
|
} XtensaMemory;
|
||||||
|
|
||||||
struct XtensaConfig {
|
struct XtensaConfig {
|
||||||
const char *name;
|
const char *name;
|
||||||
uint64_t options;
|
uint64_t options;
|
||||||
|
@ -352,6 +361,13 @@ struct XtensaConfig {
|
||||||
unsigned dcache_ways;
|
unsigned dcache_ways;
|
||||||
uint32_t memctl_mask;
|
uint32_t memctl_mask;
|
||||||
|
|
||||||
|
XtensaMemory instrom;
|
||||||
|
XtensaMemory instram;
|
||||||
|
XtensaMemory datarom;
|
||||||
|
XtensaMemory dataram;
|
||||||
|
XtensaMemory sysrom;
|
||||||
|
XtensaMemory sysram;
|
||||||
|
|
||||||
uint32_t configid[2];
|
uint32_t configid[2];
|
||||||
|
|
||||||
uint32_t clock_freq_khz;
|
uint32_t clock_freq_khz;
|
||||||
|
|
|
@ -25,9 +25,11 @@ tar -xf "$OVERLAY" -O gdb/xtensa-config.c | \
|
||||||
sed -n '1,/*\//p;/XTREG/,/XTREG_END/p' > "$TARGET"/gdb-config.c
|
sed -n '1,/*\//p;/XTREG/,/XTREG_END/p' > "$TARGET"/gdb-config.c
|
||||||
|
|
||||||
cat <<EOF > "${TARGET}.c"
|
cat <<EOF > "${TARGET}.c"
|
||||||
|
#include "qemu/osdep.h"
|
||||||
#include "cpu.h"
|
#include "cpu.h"
|
||||||
#include "exec/exec-all.h"
|
#include "exec/exec-all.h"
|
||||||
#include "exec/gdbstub.h"
|
#include "exec/gdbstub.h"
|
||||||
|
#include "qemu-common.h"
|
||||||
#include "qemu/host-utils.h"
|
#include "qemu/host-utils.h"
|
||||||
|
|
||||||
#include "core-$NAME/core-isa.h"
|
#include "core-$NAME/core-isa.h"
|
||||||
|
|
|
@ -318,6 +318,16 @@
|
||||||
.itlb = ITLB(XCHAL_HAVE_SPANNING_WAY), \
|
.itlb = ITLB(XCHAL_HAVE_SPANNING_WAY), \
|
||||||
.dtlb = DTLB(XCHAL_HAVE_SPANNING_WAY)
|
.dtlb = DTLB(XCHAL_HAVE_SPANNING_WAY)
|
||||||
|
|
||||||
|
#ifndef XCHAL_SYSROM0_PADDR
|
||||||
|
#define XCHAL_SYSROM0_PADDR 0xfe000000
|
||||||
|
#define XCHAL_SYSROM0_SIZE 0x02000000
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef XCHAL_SYSRAM0_PADDR
|
||||||
|
#define XCHAL_SYSRAM0_PADDR 0x00000000
|
||||||
|
#define XCHAL_SYSRAM0_SIZE 0x08000000
|
||||||
|
#endif
|
||||||
|
|
||||||
#elif XCHAL_HAVE_XLT_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR
|
#elif XCHAL_HAVE_XLT_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR
|
||||||
|
|
||||||
#define TLB_TEMPLATE { \
|
#define TLB_TEMPLATE { \
|
||||||
|
@ -331,6 +341,28 @@
|
||||||
.itlb = TLB_TEMPLATE, \
|
.itlb = TLB_TEMPLATE, \
|
||||||
.dtlb = TLB_TEMPLATE
|
.dtlb = TLB_TEMPLATE
|
||||||
|
|
||||||
|
#ifndef XCHAL_SYSROM0_PADDR
|
||||||
|
#define XCHAL_SYSROM0_PADDR 0x60000000
|
||||||
|
#define XCHAL_SYSROM0_SIZE 0x04000000
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef XCHAL_SYSRAM0_PADDR
|
||||||
|
#define XCHAL_SYSRAM0_PADDR 0x50000000
|
||||||
|
#define XCHAL_SYSRAM0_SIZE 0x04000000
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#else
|
||||||
|
|
||||||
|
#ifndef XCHAL_SYSROM0_PADDR
|
||||||
|
#define XCHAL_SYSROM0_PADDR 0x60000000
|
||||||
|
#define XCHAL_SYSROM0_SIZE 0x04000000
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef XCHAL_SYSRAM0_PADDR
|
||||||
|
#define XCHAL_SYSRAM0_PADDR 0x50000000
|
||||||
|
#define XCHAL_SYSRAM0_SIZE 0x04000000
|
||||||
|
#endif
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if (defined(TARGET_WORDS_BIGENDIAN) != 0) == (XCHAL_HAVE_BE != 0)
|
#if (defined(TARGET_WORDS_BIGENDIAN) != 0) == (XCHAL_HAVE_BE != 0)
|
||||||
|
@ -362,6 +394,53 @@
|
||||||
MEMCTL_ISNP | MEMCTL_DSNP | \
|
MEMCTL_ISNP | MEMCTL_DSNP | \
|
||||||
(XCHAL_HAVE_LOOPS && XCHAL_LOOP_BUFFER_SIZE ? MEMCTL_IL0EN : 0)
|
(XCHAL_HAVE_LOOPS && XCHAL_LOOP_BUFFER_SIZE ? MEMCTL_IL0EN : 0)
|
||||||
|
|
||||||
|
#define MEM_LOCATION(name, n) \
|
||||||
|
{ \
|
||||||
|
.addr = XCHAL_ ## name ## n ## _PADDR, \
|
||||||
|
.size = XCHAL_ ## name ## n ## _SIZE, \
|
||||||
|
}
|
||||||
|
|
||||||
|
#define MEM_SECTIONS(name) \
|
||||||
|
MEM_LOCATION(name, 0), \
|
||||||
|
MEM_LOCATION(name, 1), \
|
||||||
|
MEM_LOCATION(name, 2), \
|
||||||
|
MEM_LOCATION(name, 3)
|
||||||
|
|
||||||
|
#define MEM_SECTION(name) \
|
||||||
|
.num = XCHAL_NUM_ ## name, \
|
||||||
|
.location = { \
|
||||||
|
MEM_SECTIONS(name) \
|
||||||
|
}
|
||||||
|
|
||||||
|
#define SYSMEM_SECTION(name) \
|
||||||
|
.num = 1, \
|
||||||
|
.location = { \
|
||||||
|
{ \
|
||||||
|
.addr = XCHAL_ ## name ## 0_PADDR, \
|
||||||
|
.size = XCHAL_ ## name ## 0_SIZE, \
|
||||||
|
} \
|
||||||
|
}
|
||||||
|
|
||||||
|
#define LOCAL_MEMORIES_SECTION \
|
||||||
|
.instrom = { \
|
||||||
|
MEM_SECTION(INSTROM) \
|
||||||
|
}, \
|
||||||
|
.instram = { \
|
||||||
|
MEM_SECTION(INSTRAM) \
|
||||||
|
}, \
|
||||||
|
.datarom = { \
|
||||||
|
MEM_SECTION(DATAROM) \
|
||||||
|
}, \
|
||||||
|
.dataram = { \
|
||||||
|
MEM_SECTION(DATARAM) \
|
||||||
|
}, \
|
||||||
|
.sysrom = { \
|
||||||
|
SYSMEM_SECTION(SYSROM) \
|
||||||
|
}, \
|
||||||
|
.sysram = { \
|
||||||
|
SYSMEM_SECTION(SYSRAM) \
|
||||||
|
}
|
||||||
|
|
||||||
#define CONFIG_SECTION \
|
#define CONFIG_SECTION \
|
||||||
.configid = { \
|
.configid = { \
|
||||||
XCHAL_HW_CONFIGID0, \
|
XCHAL_HW_CONFIGID0, \
|
||||||
|
@ -377,6 +456,7 @@
|
||||||
TLB_SECTION, \
|
TLB_SECTION, \
|
||||||
DEBUG_SECTION, \
|
DEBUG_SECTION, \
|
||||||
CACHE_SECTION, \
|
CACHE_SECTION, \
|
||||||
|
LOCAL_MEMORIES_SECTION, \
|
||||||
CONFIG_SECTION
|
CONFIG_SECTION
|
||||||
|
|
||||||
|
|
||||||
|
@ -629,3 +709,83 @@
|
||||||
|
|
||||||
|
|
||||||
#define XTHAL_TIMER_UNCONFIGURED 0
|
#define XTHAL_TIMER_UNCONFIGURED 0
|
||||||
|
|
||||||
|
#if XCHAL_NUM_INSTROM < 1
|
||||||
|
#define XCHAL_INSTROM0_PADDR 0
|
||||||
|
#define XCHAL_INSTROM0_SIZE 0
|
||||||
|
#endif
|
||||||
|
#if XCHAL_NUM_INSTROM < 2
|
||||||
|
#define XCHAL_INSTROM1_PADDR 0
|
||||||
|
#define XCHAL_INSTROM1_SIZE 0
|
||||||
|
#endif
|
||||||
|
#if XCHAL_NUM_INSTROM < 3
|
||||||
|
#define XCHAL_INSTROM2_PADDR 0
|
||||||
|
#define XCHAL_INSTROM2_SIZE 0
|
||||||
|
#endif
|
||||||
|
#if XCHAL_NUM_INSTROM < 4
|
||||||
|
#define XCHAL_INSTROM3_PADDR 0
|
||||||
|
#define XCHAL_INSTROM3_SIZE 0
|
||||||
|
#endif
|
||||||
|
#if XCHAL_NUM_INSTROM > MAX_NMEMORY
|
||||||
|
#error XCHAL_NUM_INSTROM > MAX_NMEMORY
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if XCHAL_NUM_INSTRAM < 1
|
||||||
|
#define XCHAL_INSTRAM0_PADDR 0
|
||||||
|
#define XCHAL_INSTRAM0_SIZE 0
|
||||||
|
#endif
|
||||||
|
#if XCHAL_NUM_INSTRAM < 2
|
||||||
|
#define XCHAL_INSTRAM1_PADDR 0
|
||||||
|
#define XCHAL_INSTRAM1_SIZE 0
|
||||||
|
#endif
|
||||||
|
#if XCHAL_NUM_INSTRAM < 3
|
||||||
|
#define XCHAL_INSTRAM2_PADDR 0
|
||||||
|
#define XCHAL_INSTRAM2_SIZE 0
|
||||||
|
#endif
|
||||||
|
#if XCHAL_NUM_INSTRAM < 4
|
||||||
|
#define XCHAL_INSTRAM3_PADDR 0
|
||||||
|
#define XCHAL_INSTRAM3_SIZE 0
|
||||||
|
#endif
|
||||||
|
#if XCHAL_NUM_INSTRAM > MAX_NMEMORY
|
||||||
|
#error XCHAL_NUM_INSTRAM > MAX_NMEMORY
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if XCHAL_NUM_DATAROM < 1
|
||||||
|
#define XCHAL_DATAROM0_PADDR 0
|
||||||
|
#define XCHAL_DATAROM0_SIZE 0
|
||||||
|
#endif
|
||||||
|
#if XCHAL_NUM_DATAROM < 2
|
||||||
|
#define XCHAL_DATAROM1_PADDR 0
|
||||||
|
#define XCHAL_DATAROM1_SIZE 0
|
||||||
|
#endif
|
||||||
|
#if XCHAL_NUM_DATAROM < 3
|
||||||
|
#define XCHAL_DATAROM2_PADDR 0
|
||||||
|
#define XCHAL_DATAROM2_SIZE 0
|
||||||
|
#endif
|
||||||
|
#if XCHAL_NUM_DATAROM < 4
|
||||||
|
#define XCHAL_DATAROM3_PADDR 0
|
||||||
|
#define XCHAL_DATAROM3_SIZE 0
|
||||||
|
#endif
|
||||||
|
#if XCHAL_NUM_DATAROM > MAX_NMEMORY
|
||||||
|
#error XCHAL_NUM_DATAROM > MAX_NMEMORY
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if XCHAL_NUM_DATARAM < 1
|
||||||
|
#define XCHAL_DATARAM0_PADDR 0
|
||||||
|
#define XCHAL_DATARAM0_SIZE 0
|
||||||
|
#endif
|
||||||
|
#if XCHAL_NUM_DATARAM < 2
|
||||||
|
#define XCHAL_DATARAM1_PADDR 0
|
||||||
|
#define XCHAL_DATARAM1_SIZE 0
|
||||||
|
#endif
|
||||||
|
#if XCHAL_NUM_DATARAM < 3
|
||||||
|
#define XCHAL_DATARAM2_PADDR 0
|
||||||
|
#define XCHAL_DATARAM2_SIZE 0
|
||||||
|
#endif
|
||||||
|
#if XCHAL_NUM_DATARAM < 4
|
||||||
|
#define XCHAL_DATARAM3_PADDR 0
|
||||||
|
#define XCHAL_DATARAM3_SIZE 0
|
||||||
|
#endif
|
||||||
|
#if XCHAL_NUM_DATARAM > MAX_NMEMORY
|
||||||
|
#error XCHAL_NUM_DATARAM > MAX_NMEMORY
|
||||||
|
#endif
|
||||||
|
|
Loading…
Reference in New Issue