target/ppc: Rewrite pmu_increment_insns
Use the cached pmc_ins_cnt value. Unroll the loop over the different PMC counters. Treat the PMC4 run-latch specially. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220103224746.167831-3-danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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@ -170,45 +170,65 @@ void pmu_update_summaries(CPUPPCState *env)
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static bool pmu_increment_insns(CPUPPCState *env, uint32_t num_insns)
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{
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target_ulong mmcr0 = env->spr[SPR_POWER_MMCR0];
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unsigned ins_cnt = env->pmc_ins_cnt;
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bool overflow_triggered = false;
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int sprn;
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target_ulong tmp;
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/* PMC6 never counts instructions */
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for (sprn = SPR_POWER_PMC1; sprn <= SPR_POWER_PMC5; sprn++) {
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PMUEventType evt_type = pmc_get_event(env, sprn);
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bool insn_event = evt_type == PMU_EVENT_INSTRUCTIONS ||
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evt_type == PMU_EVENT_INSN_RUN_LATCH;
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if (pmc_is_inactive(env, sprn) || !insn_event) {
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continue;
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if (unlikely(ins_cnt & 0x1e)) {
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if (ins_cnt & (1 << 1)) {
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tmp = env->spr[SPR_POWER_PMC1];
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tmp += num_insns;
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if (tmp >= PMC_COUNTER_NEGATIVE_VAL && (mmcr0 & MMCR0_PMC1CE)) {
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tmp = PMC_COUNTER_NEGATIVE_VAL;
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overflow_triggered = true;
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}
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env->spr[SPR_POWER_PMC1] = tmp;
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}
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if (evt_type == PMU_EVENT_INSTRUCTIONS) {
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env->spr[sprn] += num_insns;
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if (ins_cnt & (1 << 2)) {
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tmp = env->spr[SPR_POWER_PMC2];
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tmp += num_insns;
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if (tmp >= PMC_COUNTER_NEGATIVE_VAL && (mmcr0 & MMCR0_PMCjCE)) {
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tmp = PMC_COUNTER_NEGATIVE_VAL;
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overflow_triggered = true;
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}
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env->spr[SPR_POWER_PMC2] = tmp;
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}
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if (evt_type == PMU_EVENT_INSN_RUN_LATCH &&
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env->spr[SPR_CTRL] & CTRL_RUN) {
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env->spr[sprn] += num_insns;
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if (ins_cnt & (1 << 3)) {
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tmp = env->spr[SPR_POWER_PMC3];
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tmp += num_insns;
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if (tmp >= PMC_COUNTER_NEGATIVE_VAL && (mmcr0 & MMCR0_PMCjCE)) {
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tmp = PMC_COUNTER_NEGATIVE_VAL;
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overflow_triggered = true;
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}
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env->spr[SPR_POWER_PMC3] = tmp;
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}
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if (env->spr[sprn] >= PMC_COUNTER_NEGATIVE_VAL &&
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pmc_has_overflow_enabled(env, sprn)) {
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if (ins_cnt & (1 << 4)) {
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target_ulong mmcr1 = env->spr[SPR_POWER_MMCR1];
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int sel = extract64(mmcr1, MMCR1_PMC4EVT_EXTR, MMCR1_EVT_SIZE);
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if (sel == 0x02 || (env->spr[SPR_CTRL] & CTRL_RUN)) {
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tmp = env->spr[SPR_POWER_PMC4];
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tmp += num_insns;
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if (tmp >= PMC_COUNTER_NEGATIVE_VAL && (mmcr0 & MMCR0_PMCjCE)) {
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tmp = PMC_COUNTER_NEGATIVE_VAL;
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overflow_triggered = true;
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}
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env->spr[SPR_POWER_PMC4] = tmp;
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}
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}
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}
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if (ins_cnt & (1 << 5)) {
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tmp = env->spr[SPR_POWER_PMC5];
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tmp += num_insns;
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if (tmp >= PMC_COUNTER_NEGATIVE_VAL && (mmcr0 & MMCR0_PMCjCE)) {
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tmp = PMC_COUNTER_NEGATIVE_VAL;
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overflow_triggered = true;
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/*
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* The real PMU will always trigger a counter overflow with
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* PMC_COUNTER_NEGATIVE_VAL. We don't have an easy way to
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* do that since we're counting block of instructions at
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* the end of each translation block, and we're probably
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* passing this value at this point.
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*
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* Let's write PMC_COUNTER_NEGATIVE_VAL to the overflowed
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* counter to simulate what the real hardware would do.
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*/
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env->spr[sprn] = PMC_COUNTER_NEGATIVE_VAL;
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}
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env->spr[SPR_POWER_PMC5] = tmp;
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}
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return overflow_triggered;
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