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55 Commits

Author SHA1 Message Date
aurel32 c55497ecb8 SH4: Remove most uses of cpu_T[0] and cpu_T[1] 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5122 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-01 13:09:21 +00:00
aurel32 7efbe24165 SH4: TCG optimisations 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5121 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-01 13:09:14 +00:00
aurel32 69d6275b00 SH4: Convert remaining non-fp ops to TCG 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5120 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-01 13:09:06 +00:00
aurel32 c047da1af4 SH4: Convert shift functions to TCG 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5119 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-30 22:37:17 +00:00
aurel32 390af82166 SH4: convert control/status register load/store to TCG 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5118 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-30 22:07:52 +00:00
aurel32 fa4da1074c SH4: Convert memory loads/stores to TCG 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5117 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-30 22:07:44 +00:00
aurel32 6f06939b68 SH4: convert some more arithmetics ops to TCG 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5116 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-30 13:55:14 +00:00
aurel32 e6afc2f4b9 SH4: convert a few helpers to TCG 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5112 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-29 23:01:41 +00:00
aurel32 1000822b03 SH4: convert branch/jump instructions to TCG 
(Shin-ichiro KAWASAKI)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5111 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-29 22:32:32 +00:00
aurel32 a46256129e SH4: convert simple compare instructions to TCG 
(Shin-ichiro KAWASAKI)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5108 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-29 20:12:18 +00:00
aurel32 3a8a44c4a8 SH4: convert a few control or system register functions to TCG 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5107 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-29 16:32:18 +00:00
aurel32 829337a687 SH4: Fix bugs introduce in r5099 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5106 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-29 16:08:38 +00:00
aurel32 5aa3b1eaf8 SH4: fix xtrct Rm,Rn (broken in r5103) 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5105 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-29 13:27:29 +00:00
aurel32 559dd74de8 SH4: convert logic and arithmetic ops to TCG 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5103 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-29 10:05:12 +00:00
aurel32 1e8864f75d SH4: use TCG variables for gregs 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5102 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-29 00:48:50 +00:00
aurel32 3bf73a4980 SH4: use uint32_t/i32 based types/ops 
Use uint32_t/i32 based types/ops to stay consistent with previous dyngen
code. Thanks to Paul Brook for noticing that.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5101 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-28 21:37:53 +00:00
aurel32 8f99cc6c3e SH4: Convert register moves to TCG 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5100 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-28 21:02:38 +00:00
aurel32 a73d39ba06 SH4: Convert dyngen registers moves to TCG 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5099 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-28 21:02:30 +00:00
aurel32 ccc9cc5bab SH4: Convert immediate loads to TCG 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5098 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-28 21:02:19 +00:00
aurel32 988d7eaa7b SH4: add support for TCG helpers 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5096 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-28 21:02:00 +00:00
aurel32 6858571c5a SH4: Init TCG variables 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5095 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-28 21:01:53 +00:00
aurel32 825c69ce02 sh4: fix tas.b @Rn instruction 
(Shin-ichiro KAWASAKI, based on a patch from Andrzej Zaborowski)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5074 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-22 21:30:28 +00:00
aurel32 7da76bcef2 [sh4] code translation bug fix 
When a TLB miss occurs while pre-decrement store instruction such as
"mov.l Rm, @-Rn" is executed, re-execution of such instruction cause
status confusion. Because pre Rn decrement is executed before TLB miss,
re-execution decrements Rn again.
In other words, in a translated instruction array, register status
should not modified before memory access instruction.

(Shin-ichiro KAWASAKI)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5069 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-22 08:58:00 +00:00
aurel32 274a9e70de [sh4] delay slot bug fix 
Two bugs about delay slot handlings are fixed.

- After an exception occurred in delay slot, the branch instruction
  before delay slot should be executed again. To judge such re-execution
  is necessery or not, delay slot status is kept in SH4 CPU data structure.
- When a branch instruction is placed at the end of memory segment,
  the delay slot is placed at the start of next memory segment.
  It means delay slot comes to the start of a translation block.
  In such occasion, DELAY_SLOT_CLAREME flag is used to transmit status
  between translation blocks. When an exception occurs on this kind of
  delay slot, DELAY_SLOT_CLEARME flag cause a status confusion in exception
  handling. DELAY_SLOT_CLEARME flag should be cleared on exceptions.

And some items are added to CPU status dump.

(Shin-ichiro KAWASAKI)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5066 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-22 08:57:35 +00:00
aurel32 833ed38689 [sh4] sleep instruction 
This patch adds sleep instruction.

(Shin-ichiro KAWASAKI)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5065 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-22 08:57:27 +00:00
blueswir1 a5f1b965da Fix warnings that would be generated by gcc -Wstrict-prototypes 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5021 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-17 20:21:51 +00:00
ths 2cfc5f17d3 Small cleanup of gen_intermediate_code(_internal), by Laurent Desnogues. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4891 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-18 18:01:29 +00:00
pbrook b2437bf267 Add missing static qualifiers. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4801 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-29 12:29:56 +00:00
pbrook 2e70f6efa8 Add instruction counter. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4799 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-29 01:03:05 +00:00
aurel32 ea2b542a4c SH4 MMU improvements 
(Shin-ichiro KAWASAKI)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4396 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-09 18:45:55 +00:00
aurel32 d2856f1ad4 Factorize code in translate.c 
(Glauber Costa)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4274 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-04-28 00:32:32 +00:00
aurel32 ca10f86763 Remove osdep.c/qemu-img code duplication 
(Kevin Wolf)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4191 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-04-11 21:35:42 +00:00
aurel32 24988dc241 SH4, fix several instructions 
fix instruction code for frchg, fschg, ocbp.
fix addressing mode handling for @Rn+, @-Rn, @(disp,gbr).
fix operation for div0s.
fix comments for mov imm, add imm, @(r0+,gbr), mac.l @Rm+,@Rn+.
fix ldb to ldub for or/tst/xor.b #imm,@(r0,gbr).
add fmov extended operations.
add fcmp/eq, fcmp/gt, fneg, fabs, fsqrt, fcnvsd, fcnvds.

(Takashi Yoshii)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4040 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-03-11 23:22:37 +00:00
bellard 57fec1fee9 use the TCG code generator 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3944 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-02-01 10:50:11 +00:00
ths 823029f909 SH4 delay slot code update, by Magnus Damm. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3761 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-12-02 06:10:04 +00:00
bellard b0b3de8988 fixed FPU rounding init 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3615 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-11-11 19:49:51 +00:00
bellard aaed909a49 added cpu_model parameter to cpu_init() 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3562 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-11-10 15:15:54 +00:00
ths c5e814b271 Fix rte opcode, by Magnus Damm. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3273 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-09-29 19:52:22 +00:00
ths 5fafdf24ef find -type f | xargs sed -i 's/[\t ]$//g' # on most files 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3173 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-09-16 21:08:06 +00:00
ths ce62e5ba09 Fix tb->size mishandling, by Daniel Jacobowitz. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3160 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-09-11 10:04:58 +00:00
ths 8c2cc7cecb SH4 mov.b fix, by Vince Weaver. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3152 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-08-26 17:48:48 +00:00
ths 022a22c7e1 Ignore PR flag in FPSCR when performing fmov, by Magnus Damm. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3005 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-06-22 11:47:05 +00:00
ths e67888a7da Document FPSCR usage, by Magnus Damm. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3004 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-06-22 11:44:41 +00:00
ths e3d8a9858e Use DREG() instead of XREG() wherever possible, by Magnus Damm. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3003 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-06-22 11:43:07 +00:00
ths ea6cf6be8e Emulate more fpu opcodes, by Magnus Damm. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3002 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-06-22 11:12:01 +00:00
ths 4c909d14c2 Set FD bit in SR to emulate kernel behaviour, by Magnus Damm. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2999 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-06-22 10:12:54 +00:00
ths f09111e088 Fix XHACK() macro and use FREG if possible, by Magnus Damm. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2815 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-05-13 16:33:43 +00:00
ths 8bf5a80475 Fix opcode for sts.l fpul/cpscr, by Magnus Damm. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2729 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-04-26 23:48:49 +00:00
ths 820e00f252 Define gen_intermediate_code_internal as "static inline". 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2512 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-03-19 21:46:06 +00:00
pbrook 9c2a9ea1b1 SH bugfixes. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1991 c046a42c-6fe2-441c-8c8c-71466251a162
 2006-06-18 19:12:54 +00:00