This patch updates the sun4u model to being much closer to a real Ultra 5
by moving devices behind the 2 simba PCI bridges (A and B) as found on real
hardware.
The most noticeable change introduced by this patchset is that in-built devices
are no longer attached to the PCI root bus, but instead behind PCI bridge A.
Along with this the interrupt routing is updated accordingly to match the
official documentation.
Since the existing code currently bypasses the PCI bridge interrupt
swizzling, the interrupt mapping functions are reorganised so that
pci_pbm_map_irq() is used by the PCI bridges and pci_apb_map_irq() is
used by the PCI host bridge.
Behind the sabre PCI host bridge, the PCI IO space now needs to be
split into two separate halves at 0x8000000. Therefore we also setup a new
PCI IO space region of increased size on the PCI host bridge and enable
32-bit PCI IO accesses to allow IO accesses to reach devices behind PCI
bridge B correctly.
As part of this change we also combine the onboard sunhme NIC and the ebus
into a single multi-function device as done on a real Ultra 5. For other
NICs the existing behaviour is preserved, i.e. we initialise them and
place them into the next free slot on PCI bus B.
Finally we mark the physically unavailable slots (plus slot 0 in busA) as
reserved to ensure that users can't plug devices into non-existent slots
which will break interrupt routing.
Note: since this commit changes PCI topology and interrupt routing, an
updated openbios-sparc64 binary is included with this commit containing the
associated changes to maintain bisectability.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Artyom Tarasenko <atar4qemu@gmail.com>
Real sun4u systems memory-map the NVRAM on the (ISA) ebus, so switch over to
MMIO from ioport access whilst setting the base year to 1968 as used by Sun
systems. This allows all SPARC64 OSs included in my tests to correctly detect
the NVRAM IC and read the hardware clock correctly upon boot.
Note that this also requires a corresponding OpenBIOS update to r1330 in order
to switch the SPARC64 NVRAM accessors over from ioport to MMIO.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
This reverts commit 10442558ab.
With the updated OpenBIOS image, -M g3beige fails to boot quik.
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-id: 1360796292-27078-1-git-send-email-agraf@suse.de
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Update OpenBIOS images to SVN r1062. Build with GCC 4.6.0
in order to avoid boot problems introduced by GCC 4.7.[01].
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Update Sparc32 and Sparc64 OpenBIOS images to SVN revision 859.
Bring also pc-bios/README up to date including the update performed by
419ef5f1c6.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
For Sparc64, this fixes the PCI bridge configuration bugs revealed by the
improved bridge handling (b7ee1603c1).
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Use firmware configuration device for boot device, kernel, initrd and
kernel command line parameters on PPC, Sparc32 and Sparc64.
Update OpenBIOS images to r479 which supports the change.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6777 c046a42c-6fe2-441c-8c8c-71466251a162
