Jia Liu
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e54a5aff13
|
target-or32: Add int instruction helpers
Add OpenRISC int instruction helpers.
Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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2012-07-27 21:12:59 +00:00 |
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Jia Liu
|
1d7d403469
|
target-or32: Add exception support
Add OpenRISC exception support.
Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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2012-07-27 21:12:58 +00:00 |
|
Jia Liu
|
b6a71ef7e0
|
target-or32: Add interrupt support
Add OpenRISC interrupt support.
Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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2012-07-27 21:12:57 +00:00 |
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Jia Liu
|
726fe04572
|
target-or32: Add MMU support
Add OpenRISC MMU support.
Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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2012-07-27 21:12:56 +00:00 |
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Jia Liu
|
e67db06e9f
|
target-or32: Add target stubs and QOM cpu
Add OpenRISC target stubs, QOM cpu and basic machine.
Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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2012-07-27 21:12:55 +00:00 |