Commit Graph

2856 Commits

Author SHA1 Message Date
Peter Maydell b72566a4ff Trivial patches (2018-12-18)
-----BEGIN PGP SIGNATURE-----
 
 iQIcBAABAgAGBQJcGQQZAAoJEPMMOL0/L7480Q8QAJq1KW6pywJ8vKMDbDaDOgZw
 GwF8iKVtHCPClmDk3W7HHMRr1Ef9rwRrt/mdjzOehBSCep0J2PmPnqul/EXra0ot
 efyq6q20n1epordI3HuOTKqqvBkt7EUg2sqCWnHzT3qFe7FaZLnrJqChsm8B6psU
 IWTlaVNAo50J17TYo88UhIuME5WRZ9mdoiPEZ9pyvFaVrDKCnKZz1QPsqcjEJL1S
 sfLUhGrk8C03ZR7DG4ruULhF+tqYYT+vKTVNkL+1IvWHl3IIVJadC2yxPduH1JT4
 TLPAfRqpw4yjL/E6X3HMrDBeMd2H2bMRgTMapFFegaA9XPrvo5wJJoxix2WZ7Yw3
 efasQtRfZnh69GK2M81//G+61TnO0iDWDJmSjuo9IXrmJ29x2IqmZyqr8DlZ+bPd
 2+qRN4WrSfcTSJMqpMcP4tILAG53XvQ0xY4jJkQQZk4QHxWhlcmIQ+hLw0rE+NQj
 sTBLGvnIZ6nzWC5MVa1cAVXr52hyZhhElEVWEgxJ5vwDop5K3XZnEd0w7DMTEJpr
 lBLpWC0g8zn2xSy47KzrVVV5bJ/khm2M2X9y6XXHg1sft3DwUdgeBVwRGkDxir8P
 92UoIaur+xeYPj4eSvz8Bcx2lLktSOOFgNMsWCnMhxxVCkrCbT0Nt8UEFyn594xL
 gPPcBtYh3ryoGFLk7WRK
 =xjtK
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/vivier2/tags/trivial-patches-pull-request' into staging

Trivial patches (2018-12-18)

# gpg: Signature made Tue 18 Dec 2018 14:28:41 GMT
# gpg:                using RSA key F30C38BD3F2FBE3C
# gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>"
# gpg:                 aka "Laurent Vivier <laurent@vivier.eu>"
# gpg:                 aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>"
# Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F  5173 F30C 38BD 3F2F BE3C

* remotes/vivier2/tags/trivial-patches-pull-request:
  error: Remove NULL checks on error_propagate() calls
  vl: Use error_fatal to simplify obvious fatal errors (again)
  i386: hvf: drop debug printf in decode_sldtgroup
  docs/devel/build-system: fix 'softmu' typo

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-12-19 15:31:02 +00:00
Roman Bolshakov bcdc508190 i386: hvf: drop debug printf in decode_sldtgroup
It's going to clutter QEMU logs if 0x0f00 is trapped.

Signed-off-by: Roman Bolshakov <r.bolshakov@yadro.com>
Message-Id: <20181203100415.53027-2-r.bolshakov@yadro.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-12-18 14:57:48 +01:00
Emilio G. Cota b8c547000d target/tricore: use float32_is_denormal
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2018-12-17 08:25:25 +00:00
Peter Maydell b019f5e537 miscellaneous patches:
* checkpatch.pl: Enforce multiline comment syntax
  * Rename cpu_physical_memory_write_rom() to address_space_write_rom()
  * disas, monitor, elf_ops: Use address_space_read() to read memory
  * Remove load_image() in favour of load_image_size()
  * Fix some minor memory leaks in arm boards/devices
  * virt: fix broken indentation
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABCAAGBQJcE8EQAAoJEDwlJe0UNgze1iAP/3HAQI4Z5A3pX3I2YnVBDrS3
 hOsPXNUNs2asDqoijkq4cxaqhTv1bio7CPLTg8uvkyWiCOS6pbKjtlE+A/VKGjKZ
 7rH9GBNxlH7h/ZIRJTPfX38YiAWI//eIRY4JqUgKpmprE6Y7cGf5/uzmE0OwBwur
 HlKKkox6oH4WEk6rTIqP92xMhJNuTC2j1s7qQ2dCQKZdNAAYh++cHuiR1JtEjeQ8
 O1/O4u6lumnqQMFtqhlt5++QxWvBU5IbdyJblBV+hCQekNSkj5fUIequBsjGrJru
 aZGxO828EEM7dS9/fFnT+YU25/rJ43RSs8aSBLqI/WWRALGQKU88POS5T7zfpzq/
 3qzSPWrOhgMFxl/APrGi13DdXTZ5J9UA0qypL8RiwdWj6WWJOo1OcRqzMGQhv1HS
 Fe22cWDDuXimQhUuyXM/XY234iPxFJkkq89ANHHfeCNFurzNV9WVN1mV2pfqwdX0
 khh3DZyXRDa/UazLY0QyJHStyop76Ox8P8tCAvQbhZWr33Ns+uTr1YBHibimx3iG
 6FOpH0FcpAE9oab9xUIdtMJCtx0YEWQ0ap/xMLlnmS8/bL7PX8HY0SIT2WwAiybg
 ibwen23Aah5LPpvd5BjGi1MAQEQwZvX8Ab7G+h1F4yzSfOchQt3eZN4fhwOkgjQA
 Bbb3bFUkIcXZ8BqabHA8
 =ehNF
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-misc-20181214' into staging

miscellaneous patches:
 * checkpatch.pl: Enforce multiline comment syntax
 * Rename cpu_physical_memory_write_rom() to address_space_write_rom()
 * disas, monitor, elf_ops: Use address_space_read() to read memory
 * Remove load_image() in favour of load_image_size()
 * Fix some minor memory leaks in arm boards/devices
 * virt: fix broken indentation

# gpg: Signature made Fri 14 Dec 2018 14:41:20 GMT
# gpg:                using RSA key 3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>"
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-misc-20181214: (22 commits)
  virt: Fix broken indentation
  target/arm: Create timers in realize, not init
  tests/test-arm-mptimer: Don't leak string memory
  hw/sd/sdhci: Don't leak memory region in sdhci_sysbus_realize()
  hw/arm/mps2-tz.c: Free mscname string in make_dma()
  target/arm: Free name string in ARMCPRegInfo hashtable entries
  include/hw/loader.h: Document load_image_size()
  hw/core/loader.c: Remove load_image()
  device_tree.c: Don't use load_image()
  hw/block/tc58128.c: Don't use load_image()
  hw/i386/multiboot.c: Don't use load_image()
  hw/i386/pc.c: Don't use load_image()
  hw/pci/pci.c: Don't use load_image()
  hw/smbios/smbios.c: Don't use load_image()
  hw/ppc/ppc405_boards: Don't use load_image()
  hw/ppc/mac_newworld, mac_oldworld: Don't use load_image()
  elf_ops.h: Use address_space_write() to write memory
  monitor: Use address_space_read() to read memory
  disas.c: Use address_space_read() to read memory
  Rename cpu_physical_memory_write_rom() to address_space_write_rom()
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-12-16 16:32:43 +00:00
Peter Maydell 397cd31f01 target/arm: Create timers in realize, not init
The timer_new() function allocates memory; this means that
if we call it in the CPU's init method we would need
to provide an instance_finalize method to free it. Defer
the timer creation to the realize function instead.

This fixes a memory leak spotted by clang LeakSanitizer
when a CPU object is created for introspection.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181204132952.2601-6-peter.maydell@linaro.org
2018-12-14 13:30:55 +00:00
Peter Maydell ac87e5072e target/arm: Free name string in ARMCPRegInfo hashtable entries
When we add a new entry to the ARMCPRegInfo hash table in
add_cpreg_to_hashtable(), we allocate memory for tehe
ARMCPRegInfo struct itself, and we also g_strdup() the
name string. So the hashtable's value destructor function
must free the name string as well as the struct.

Spotted by clang's leak sanitizer. The leak here is a
small one-off leak at startup, because we don't support
CPU hotplug, and so the only time when we destroy
hash table entries is for the case where ARM_CP_OVERRIDE
means we register a wildcard entry and then override it later.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20181204132952.2601-2-peter.maydell@linaro.org
2018-12-14 13:30:53 +00:00
Richard Henderson 2d7137c10f target/arm: Implement the ARMv8.1-LOR extension
Provide a trivial implementation with zero limited ordering regions,
which causes the LDLAR and STLLR instructions to devolve into the
LDAR and STLR instructions from the base ARMv8.0 instruction set.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181210150501.7990-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-12-13 14:41:24 +00:00
Richard Henderson 7c208e0f41 target/arm: Use arm_hcr_el2_eff more places
Since arm_hcr_el2_eff includes a check against
arm_is_secure_below_el3, we can often remove a
nearby check against secure state.

In some cases, sort the call to arm_hcr_el2_eff
to the end of a short-circuit logical sequence.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181210150501.7990-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-12-13 14:41:24 +00:00
Richard Henderson f777844460 target/arm: Introduce arm_hcr_el2_eff
Replace arm_hcr_el2_{fmo,imo,amo} with a more general routine
that also takes SCR_EL3.NS (aka arm_is_secure_below_el3) into
account, as documented for the plethora of bits in HCR_EL2.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181210150501.7990-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-12-13 14:41:24 +00:00
Richard Henderson ab638a328f target/arm: Implement the ARMv8.2-AA32HPD extension
The bulk of the work here, beyond base HPD, is defining the
TTBCR2 register.  In addition we must check TTBCR.T2E, which
is not present (RES0) for AArch64.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181203203839.757-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-12-13 14:41:24 +00:00
Richard Henderson 037c13c590 target/arm: Implement the ARMv8.1-HPD extension
Since the TCR_*.HPD bits were RES0 in ARMv8.0, we can simply
interpret the bits as if ARMv8.1-HPD is present without checking.
We will need a slightly different check for hpd for aarch32.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181203203839.757-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-12-13 14:41:24 +00:00
Richard Henderson ea22747c63 target/arm: Tidy scr_write
Because EL3 has a fixed execution mode, we can properly decide
which of the bits are RES{0,1}.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181203203839.757-8-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-12-13 14:41:24 +00:00
Richard Henderson 619959c358 target/arm: Fix HCR_EL2.TGE check in arm_phys_excp_target_el
The enable for TGE has already occurred within arm_hcr_el2_amo
and friends.  Moreover, when E2H is also set, the sense is
supposed to be reversed, which has also already occurred within
the helpers.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181203203839.757-5-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-12-13 14:41:24 +00:00
Richard Henderson 99f8f86d36 target/arm: Add SCR_EL3 bits up to ARMv8.5
Post v8.4 bits taken from SysReg_v85_xml-00bet8.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181203203839.757-4-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-12-13 14:41:24 +00:00
Richard Henderson 099bf53b7a target/arm: Add HCR_EL2 bits up to ARMv8.5
Post v8.3 bits taken from SysReg_v85_xml-00bet8.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181203203839.757-3-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-12-13 14:41:24 +00:00
Peter Maydell 3dc91ddbc6 target/arm: Move id_aa64mmfr* to ARMISARegisters
At the same time, define the fields for these registers,
and use those defines in arm_pamax().

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181203203839.757-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: fixed up typo (s/achf/ahcf/) belatedly spotted by RTH]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-12-13 14:40:56 +00:00
Peter Maydell 8be76cf17b x86 queue, 2018-12-11
* New CPU features: MOVDIRI, MOVDIR64B (Liu Jingqi);
   STIBP (Eduardo Habkost)
 * Fix clang build warning (Peter Maydell)
 -----BEGIN PGP SIGNATURE-----
 
 iQIcBAABCAAGBQJcECOoAAoJECgHk2+YTcWmVJEP/i84W3cxiB512E04qB7hLFkB
 R+S+oZfwflQRslJjJugwNl69YrrCJc/w+0k+ly2fNyDAv0WqiHnfC0EFhUc/kNLG
 wP5RA7i9Y+ZQDHtSJGF4Wre4wfzb6+2y057DEx9pddnEIpkyTudPsoK81HyTBwfZ
 DIn1QizmjL78+PAe4JY08jz1Rp+fjmvaFrRiIx5RWqZ/ojcSHdUvltjhzx+rleuT
 lx2Ra95ZH5OYHHEMFT55wpjhmm+Q2qa/RnwJyFCuQEpa/23Vy2hEKNNz6mgQpVux
 EzQ8VH8rtqYPwzAwnd9XWUYP/W5OPUrxWmJbGe3MygNIgGv5IUbJC8pkb2v1bRJB
 URZD6hSG2LcTIuZsnKvE1oSBATbkCRrmDhmQXmz4ZzIFh89r8MsJqYkfIzfhEh5L
 DM2I80kNp/vj2/WH5HIeDkJb0DP2YsFA9yyEF82Dqt/0mBYCBx+u3JsljnEhMRi1
 v1ul1a6+qjp+tTsCdI4nJ3dpjO5RDtYZ5d/gD+wEuB0yOSTUqoPbHOP4iXlWyq8Z
 85r7/rtE68Vura7M6gwXjO3/rc/G5Tj0bd74yZsEmoMh9ZaxuIwPAWyo198uamp+
 esl5GqnfUv+UcyuMQup8KGVQGh9MxBfEbigmbpfGvTpAALzWhZ80dS7lPZ6923+u
 DpY1coadtgsIRVHbLSWN
 =24BF
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/ehabkost/tags/x86-next-pull-request' into staging

x86 queue, 2018-12-11

* New CPU features: MOVDIRI, MOVDIR64B (Liu Jingqi);
  STIBP (Eduardo Habkost)
* Fix clang build warning (Peter Maydell)

# gpg: Signature made Tue 11 Dec 2018 20:52:56 GMT
# gpg:                using RSA key 2807936F984DC5A6
# gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>"
# Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF  D1AA 2807 936F 984D C5A6

* remotes/ehabkost/tags/x86-next-pull-request:
  i386: Add "stibp" flag name
  target/i386/kvm.c: Don't mark cpuid_data as QEMU_PACKED
  x86/cpu: Enable MOVDIR64B cpu feature
  x86/cpu: Enable MOVDIRI cpu feature

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-12-12 21:11:49 +00:00
Peter Maydell 4b3aab2042 Trivial patches (2018-12-11)
-----BEGIN PGP SIGNATURE-----
 
 iQIcBAABAgAGBQJcD/usAAoJEPMMOL0/L748br0P/iLL5RjzHJ+vrBsphRNPZ0eM
 1wvgWJwvo+4JicebsnTWDmElprgetu2+disXyxSJhBOllSb7lwmxKR2OyHlicu5x
 RDSk3CTZZuI/CqN08MlEVZiCuCT1LZuJ8Y0RzXBAsJlT51ZpvwprbXO1oyMjjx2P
 UhXFuYIa8Wk+8+zuFnYI4nKPo3o8ra8OrtI2AdIneQ8zWEMvJCWhHqrZHeyuHOzb
 N5bYEXi3JSIT2qyHyZlFNmXjPCNuMxhrrBc1yjmo6KJgHkVUgvn61hdod4BzvLsd
 DWAfdEamBgP4HuU2fUTVFAYXirK+A4tM+ROblJ/Z/V7RHifoulrdedQzrqdM7FA5
 6f4SUo+SSjqY1CYnS+zXp5USu6/ciaYZv9jE7W0WKjXt5kCsy9rlT0V8Q4RlOQji
 ZoT6LpcVj0qnfdPdYwdWgpqWbr8G5Y3Xm91a+XLSqzj+xfFJQ6h7fCnF1/Ngn0Ep
 o3LOtiJCDSma4maFemV7qhWfuaa20vUwfbRKeOvnTirDUv6oXpsP19kScbH06DeD
 Hs9aFgi7XmFWNypWHeZNqy00UwiZmb2GcpqL/vAVwkqdMTgttfBdh5P4srRwwM2D
 OQROJaHaBya8mzDO7BldapQOGXRHu9UDCP9gkK+BGGu4Edu0U+eRL/08GoFRM1M4
 ra2Dn/AQTIW6lk0N9He0
 =+od8
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/vivier2/tags/trivial-patches-pull-request' into staging

Trivial patches (2018-12-11)

# gpg: Signature made Tue 11 Dec 2018 18:02:20 GMT
# gpg:                using RSA key F30C38BD3F2FBE3C
# gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>"
# gpg:                 aka "Laurent Vivier <laurent@vivier.eu>"
# gpg:                 aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>"
# Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F  5173 F30C 38BD 3F2F BE3C

* remotes/vivier2/tags/trivial-patches-pull-request: (30 commits)
  Fixes i386 xchgq test
  maint: Grammar fix to mailmap
  MAINTAINERS: Update email address for Fam Zheng
  cutils: Assert in-range base for string-to-integer conversions
  util: vfio-helpers: use ARRAY_SIZE in qemu_vfio_init_pci()
  target: hax: fix errors in comment
  MAINTAINERS: Use my work email to review Build and test automation patches
  MAINTAINERS: Add a missing entry for the NVDIMM device
  MAINTAINERS: Add a missing entry to the QMP section
  MAINTAINERS: Add a missing entry to SPICE
  MAINTAINERS: Add missing entries for the MPS2 machine
  MAINTAINERS: Add missing entries for the Canon DIGIC machine
  MAINTAINERS: Add missing entries to the vhost section
  MAINTAINERS: Add missing entries to the PC Chipset section
  MAINTAINERS: Add a missing entry for the sun4m machines
  MAINTAINERS: Add a missing entry for the Old World machines
  MAINTAINERS: Add a missing entry for the Xilinx S3A-DSP 1800 machine
  MAINTAINERS: Add missing entries for the Jazz machine
  MAINTAINERS: Add missing entries for the Xilinx ZynqMP machine
  MAINTAINERS: Add a missing entry to the SPARC CPU
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-12-11 22:26:44 +00:00
Eduardo Habkost 0e89165829 i386: Add "stibp" flag name
The STIBP flag may be supported by the host KVM module, so QEMU
can allow it to be configured manually, and it can be exposed to
guests when using "-cpu host".

No additional migration code is required because the whole
contents of spec_ctrl is already migrated in the "cpu/spec_ctrl"
section.

Corresponding KVM patch was submitted at:
https://lore.kernel.org/lkml/20181205191956.31480-1-ehabkost@redhat.com/

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Message-Id: <20181210180250.31299-1-ehabkost@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-12-11 18:50:48 -02:00
Peter Maydell 9115bb1213 target/i386/kvm.c: Don't mark cpuid_data as QEMU_PACKED
clang complains about taking the address of a packed
member of a struct:

target/i386/kvm.c:1245:27: warning: taking address of packed member 'cpuid' of class or structure '' may result in an unaligned pointer value [-Waddress-of-packed-member]
    c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
                          ^~~~~~~~~~~~~~~~
target/i386/kvm.c:1297:31: warning: taking address of packed member 'cpuid' of class or structure '' may result in an unaligned pointer value [-Waddress-of-packed-member]
        c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
                              ^~~~~~~~~~~~~~~~

The kernel's definitions of struct kvm_cpuid2 and struct
kvm_cpuid_entry2 are carefully set up with padding fields
so that there is no between-struct padding anyway, so
the QEMU_PACKED annotation is unnecessary and might result
in the compiler generating worse code. Drop it, and instead
assert at build time that there is no stray padding.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20181210114654.31433-1-peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-12-11 18:50:48 -02:00
Liu Jingqi 1c65775ffc x86/cpu: Enable MOVDIR64B cpu feature
MOVDIR64B moves 64-bytes as direct-store with 64-bytes write atomicity.
Direct store is implemented by using write combining (WC) for writing
data directly into memory without caching the data.

The bit definition:
CPUID.(EAX=7,ECX=0):ECX[bit 28] MOVDIR64B

The release document ref below link:
https://software.intel.com/sites/default/files/managed/c5/15/\
architecture-instruction-set-extensions-programming-reference.pdf

Cc: Xu Tao <tao3.xu@intel.com>
Signed-off-by: Liu Jingqi <jingqi.liu@intel.com>
Message-Id: <1541488407-17045-3-git-send-email-jingqi.liu@intel.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-12-11 18:50:48 -02:00
Liu Jingqi 24261de491 x86/cpu: Enable MOVDIRI cpu feature
MOVDIRI moves doubleword or quadword from register to memory through
direct store which is implemented by using write combining (WC) for
writing data directly into memory without caching the data.

The bit definition:
CPUID.(EAX=7,ECX=0):ECX[bit 27] MOVDIRI

The release document ref below link:
https://software.intel.com/sites/default/files/managed/c5/15/\
architecture-instruction-set-extensions-programming-reference.pdf

Cc: Xu Tao <tao3.xu@intel.com>
Signed-off-by: Liu Jingqi <jingqi.liu@intel.com>
Message-Id: <1541488407-17045-2-git-send-email-jingqi.liu@intel.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-12-11 18:50:48 -02:00
Marc-André Lureau aa1b35b975 qom: make interface types abstract
Interfaces don't have instance, let's make the interface type really
abstract to avoid confusion.

Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
Message-Id: <20181204142023.15982-3-marcandre.lureau@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-12-11 15:45:22 -02:00
Li Qiang 1d4f78e93a target: hax: fix errors in comment
Cc: qemu-trivial@nongnu.org

Signed-off-by: Li Qiang <liq3ea@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <1543312812-2929-1-git-send-email-liq3ea@gmail.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-12-11 18:28:47 +01:00
Li Qiang 090627a9d9 target: hax: replace g_malloc with g_new0
And also the g_malloc doesn't need check return value,
remove it.

Cc: qemu-trivial@nongnu.org

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Li Qiang <liq3ea@gmail.com>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <1543226179-5135-1-git-send-email-liq3ea@gmail.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-12-11 18:28:46 +01:00
Marc-André Lureau df68a7f3c8 misc: fix spelling
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Message-Id: <20181105135400.18366-1-marcandre.lureau@redhat.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2018-12-11 18:28:46 +01:00
Roman Bolshakov 83ea23cd20 i386: hvf: Fix overrun of _decode_tbl1
Single opcode instructions in ff group were incorrectly processed
because an overrun of _decode_tbl1[0xff] resulted in access of
_decode_tbl2[0x0]. Thus, decode_sldtgroup was called instead of
decode_ffgroup:
  7d71: decode_sldtgroup: 1
  Unimplemented handler (7d71) for 108 (ff 0)

While at it correct maximum length for _decode_tbl2 and _decode_tbl3.

Signed-off-by: Roman Bolshakov <r.bolshakov@yadro.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-12-03 15:09:55 +00:00
Thomas Huth 3f2f3b33db target/arm/sve_helper: Fix compilation with clang 3.4
Clang 3.4 does not know the "flatten" attribute yet. We've already
introduced the QEMU_FLATTEN macro for this in commit 97ff87c0ed,
so use this macro now here, too, to fix this issue.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-id: 1543399094-2260-1-git-send-email-thuth@redhat.com
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-11-28 15:31:15 +00:00
Richard Henderson e84fcd7f66 target/i386: Generate #UD when applying LOCK to a register destination
Fixes a TCG crash due to attempting the atomic operation without
having set up the address first.  This does not attempt to fix
all of the other missing checks for LOCK.

Fixes: a7cee522f3
Fixes: https://bugs.launchpad.net/qemu/+bug/1803160
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20181113193510.24862-1-richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-11-27 15:35:19 +01:00
Marc-André Lureau 03fee66fde vmstate: constify VMStateField
Because they are supposed to remain const.

Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20181114132931.22624-1-marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-11-27 15:35:15 +01:00
Paolo Bonzini 5aaac46793 migration: savevm: consult migration blockers
There is really no difference between live migration and savevm, except
that savevm does not require bdrv_invalidate_cache to be implemented
by all disks.  However, it is unlikely that savevm is used with anything
except qcow2 disks, so the penalty is small and worth the improvement
in catching bad usage of savevm.

Only one place was taking care of savevm when adding a migration blocker,
and it can be removed.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-11-27 15:06:14 +01:00
Paolo Bonzini d98f26073b target/i386: kvm: add VMX migration blocker
Nested VMX does not support live migration yet.  Add a blocker
until that is worked out.

Nested SVM only does not support it, but unfortunately it is
enabled by default for -cpu host so we cannot really disable it.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2018-11-27 15:06:14 +01:00
Bandan Das aec5e9c3a9 kvm: Use KVM_GET_MSR_INDEX_LIST for MSR_IA32_ARCH_CAPABILITIES support
When writing to guest's MSR_IA32_ARCH_CAPABILITIES, check whether it's
supported in the guest using the KVM_GET_MSR_INDEX_LIST ioctl.

Fixes: d86f963694
Suggested-by: Eduardo Habkost <ehabkost@redhat.com>
Tested-by: balducci@units.it
Signed-off-by: Bandan Das <bsd@redhat.com>
Message-Id: <jpg4lc4iiav.fsf_-_@linux.bootlegged.copy>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2018-11-26 13:00:38 -02:00
Max Filippov 7da9111e77 target/xtensa: drop num_[core_]regs from dc232b/dc233c configs
Now that xtensa_count_regs does the right thing, remove manual
initialization of these fields from the affected configurations and let
xtensa_finalize_config initialize them. Add XTREG_END to terminate
register lists.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-11-20 12:20:41 -08:00
Max Filippov 4614f0f8bd target/xtensa: gdbstub fix register counting
In order to communicate correctly with gdb xtensa gdbstub must provide
expected number of registers in 'g' packet response. xtensa-elf-gdb
expects both nonprivileged and privileged registers. xtensa-linux-gdb
only expects nonprivileged registers. gdb only counts one contiguous
stretch of registers, do the same for the core registers in the
xtensa_count_regs.

With this change qemu-system-xtensa is able to communicate with all
xtensa-elf-gdb versions (versions prior to 8.2 require overlay fixup),
and qemu-xtensa is able to communicate with all xtensa-linux-gdb
versions, except 8.2.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-11-20 12:20:41 -08:00
Luc Michel 7760da729a target/arm: fix smc incorrectly trapping to EL3 when secure is off
This commit fixes a case where the CPU would try to go to EL3 when
executing an smc instruction, even though ARM_FEATURE_EL3 is false. This
case is raised when the PSCI conduit is set to smc, but the smc
instruction does not lead to a valid PSCI call.

QEMU crashes with an assertion failure latter on because of incoherent
mmu_idx.

This commit refactors the pre_smc helper by enumerating all the possible
way of handling an scm instruction, and covering the previously missing
case leading to the crash.

The following minimal test would crash before this commit:

.global _start
    .text
_start:
    ldr x0, =0xdeadbeef  ; invalid PSCI call
    smc #0

run with the following command line:

aarch64-linux-gnu-gcc -nostdinc -nostdlib -Wl,-Ttext=40000000 \
                      -o test test.s

qemu-system-aarch64 -M virt,virtualization=on,secure=off \
                    -cpu cortex-a57 -kernel test

Signed-off-by: Luc Michel <luc.michel@greensocs.com>
Message-id: 20181117160213.18995-1-luc.michel@greensocs.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-11-19 15:29:08 +00:00
Richard Henderson 3c3efcf7da target/arm: Fill in ARMISARegisters for kvm32
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181113180154.17903-5-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-11-19 15:29:08 +00:00
Richard Henderson b653c55fa7 target/arm: Introduce read_sys_reg32 for kvm32
Assert that the value to be written is the correct size.
No change in functionality here, just mirroring the same
function from kvm64.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181113180154.17903-4-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-11-19 15:29:07 +00:00
Richard Henderson 9d60dea960 target/arm: Fill in ARMISARegisters for kvm64
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181113180154.17903-3-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-11-19 15:29:07 +00:00
Richard Henderson 4674097c32 target/arm: Install ARMISARegisters from kvm host
The ID registers are replacing (some of) the feature bits.
We need (some of) these values to determine the set of data
to be handled during migration.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181113180154.17903-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-11-19 15:29:07 +00:00
Peter Maydell d1b3b1ee9d MIPS queue for QEMU 3.1-rc2 - v2
-----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQEcBAABAgAGBQJb8F5WAAoJENSXKoln91plAtoH/1aBwQbI8BhiKDxD1KZOSQMD
 Sefn15AuRECfM2Helfzr/3rHPhXa7OWCjI10Z7pNMxAy3wpAjPec6eeVzfRx0xDJ
 3vIkUuFQCzjHl5BloKdlsRPJC2/mTrwtvpLUF8g3D/pUpZoLyMF5f1mo4tVn9yz3
 TRRajkLIRaPJQ3aA/q4BJYYYebVD7treLi+HGMhvRYQmdcaVZAXvGsYnAHIHqU6u
 jNJm6w15SkoqR7u8/7rVrLLdR8jyB7XfBK7uih9O5kYcdkH5oa8QEE2khYtRfPw0
 g2MmYmGSnZKQzCWK0aGzNhnP5QPgjy733WmbnLKqnelKvYnV74B1ZCuoA1J6bX0=
 =2r8m
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-november-2018-v2' into staging

MIPS queue for QEMU 3.1-rc2 - v2

# gpg: Signature made Sat 17 Nov 2018 18:30:46 GMT
# gpg:                using RSA key D4972A8967F75A65
# gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01  DD75 D497 2A89 67F7 5A65

* remotes/amarkovic/tags/mips-queue-november-2018-v2:
  MAINTAINERS: Add Stefan Markovic as a MIPS reviewer
  target/mips: Disable R5900 support
  target/mips: Rename MMI-related functions
  target/mips: Rename MMI-related opcodes
  target/mips: Rename MMI-related masks
  target/mips: Guard check_insn with INSN_R5900 check
  target/mips: Guard check_insn_opc_user_only with INSN_R5900 check
  target/mips: Fix decoding mechanism of special R5900 opcodes
  target/mips: Fix decoding mechanism of R5900 DIV1 and DIVU1
  target/mips: Fix decoding mechanism of R5900 MFLO1, MFHI1, MTLO1 and MTHI1
  linux-user: Update MIPS specific prctl() implementation

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-11-19 10:23:45 +00:00
Aleksandar Markovic 823f2897bd target/mips: Disable R5900 support
Disable R5900 support. There are some outstanding issues related
to ABI support and emulation accuracy, that were not understood
well during review process. Disable to avoid backward compatibility
issues.

Reverts commit ed4f49ba9b.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-11-17 19:29:34 +01:00
Aleksandar Markovic 874b287970 target/mips: Rename MMI-related functions
Rename MMI-related functions.

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-11-17 19:29:34 +01:00
Aleksandar Markovic baa609db75 target/mips: Rename MMI-related opcodes
Rename MMI-related opcodes.

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-11-17 19:29:34 +01:00
Aleksandar Markovic c8341e0000 target/mips: Rename MMI-related masks
Rename MMI-related masks.

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-11-17 19:29:34 +01:00
Fredrik Noring 992e8176d3 target/mips: Guard check_insn with INSN_R5900 check
Explicitely mark handling of PREF instruction for R5900 as
treating the same as NOP.

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Fredrik Noring <noring@nocrew.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-11-17 19:29:34 +01:00
Fredrik Noring 55fc7a69aa target/mips: Guard check_insn_opc_user_only with INSN_R5900 check
Avoid using check_opc_user_only() as a decision making code wrt
various architectures. Use ctx->insn_flags checks instead.

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Fredrik Noring <noring@nocrew.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-11-17 19:29:34 +01:00
Fredrik Noring 9dc324ce66 target/mips: Fix decoding mechanism of special R5900 opcodes
MOVN, MOVZ, MFHI, MFLO, MTHI, MTLO, MULT, MULTU, DIV, DIVU, DMULT,
DMULTU, DDIV, DDIVU and JR are decoded in decode_opc_special_tx79
instead of the generic decode_opc_special_legacy.

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Fredrik Noring <noring@nocrew.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-11-17 19:29:34 +01:00
Fredrik Noring c42171c3bf target/mips: Fix decoding mechanism of R5900 DIV1 and DIVU1
DIV1 and DIVU1 are generated in gen_div1_tx79 instead of the generic
gen_muldiv.

Signed-off-by: Fredrik Noring <noring@nocrew.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-11-17 19:29:34 +01:00
Fredrik Noring 86efbfb619 target/mips: Fix decoding mechanism of R5900 MFLO1, MFHI1, MTLO1 and MTHI1
MFLO1, MFHI1, MTLO1 and MTHI1 are generated in gen_HILO1_tx79 instead of
the generic gen_HILO.

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Fredrik Noring <noring@nocrew.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2018-11-17 19:29:34 +01:00