The beginning of the register allocation order list on the TCG x86_64
target matches the list of clobbered registers. This means that when an
helper is called, there is almost always clobbered registers that have
to be spilled.
The same way register %rsi and %rdi are at the top of the register
allocation order list, while they can't be used for load/store
operations. This means the data and/or address registers are very often
%rsi and %rdi, and their values have to be spilled, and then moved back
to another register.
This patches changes to the allocation order to avoid those effects.
It results in a 8% gain speed in qemu-x86_64 to compress a bzip2 file,
and a 6% gain in qemu-system-mips64 to compile a small application.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7003 c046a42c-6fe2-441c-8c8c-71466251a162
Rename bswap_i32 into bswap32_i32 and bswap_i64 into bswap64_i64
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6829 c046a42c-6fe2-441c-8c8c-71466251a162
Remove definitions for TCG_AREGs corresponding to AREG definitions
removed in r6778.
Signed-off-by: Stuart Brady <stuart.brady@gmail.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6779 c046a42c-6fe2-441c-8c8c-71466251a162
Starting with version 4.3, gcc returns the result of a function in
rax/eax/ax/al instead of rax/eax, depending of the return type. As
a consequence we should use a zero extend moe in TCG loads/stores.
See http://gcc.gnu.org/ml/gcc/2008-01/msg00052.html for more details.
A big thanks to malc who founds the problem and wrote the x86 patch.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6011 c046a42c-6fe2-441c-8c8c-71466251a162
