Commit Graph

141 Commits

Author SHA1 Message Date
Alexander Graf ad8a4570ad target-s390x: wire up I/O instructions in TCG mode
The code handling the I/O instructions for KVM decodes the instruction
itself. In TCG mode also pass the full instruction word to the helpers.

Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-17 12:40:50 +02:00
Aurelien Jarno 8df7eef305 target-s390x: wire up DIAG IPL in TCG mode
DIAG IPL is already implemented for KVM, but not wired from TCG. For
that change the format of the instruction so that we can get R1 and R3
numbers in addition to the function code.

The diag function can change plenty of things, including CC, so we
should enter with a static CC. Also it doesn't set the value of general
register 2 to 0 as in the current code. We also need to exit the CPU
loop after a reset, which means a new PSW.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-17 12:40:50 +02:00
Aurelien Jarno a1f12d855b target-s390x: implement high-word facility
Besides RISBHG and RISBLG, all high-word instructions are not
implemented. Fix that.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-05 01:37:59 +02:00
Aurelien Jarno 782a847952 target-s390x: implement load-and-trap facility
At the same time move the trap code from op_ct into gen_trap and use it
for all new functions. The value needs to be stored back to register
before the exception, but also before the brcond (as we don't use
temp locals). That's why we can't use wout helper.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-05 01:37:59 +02:00
Aurelien Jarno 375ee58bed target-s390x: implement miscellaneous-instruction-extensions facility
RISBGN is the same as RISBG, but without setting the condition code.
CLT and CLGT are the same as CLRT and CLGRT, but using memory for the
second operand.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-05 01:37:59 +02:00
Aurelien Jarno df46283ce7 target-s390x: implement LPDFR and LNDFR instructions
This complete the floating point support sign handling facility.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-05 01:37:59 +02:00
Aurelien Jarno 3f4de6756c target-s390x: implement TRANSLATE EXTENDED instruction
It is part of the basic zArchitecture instructions.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-05 01:37:59 +02:00
Aurelien Jarno 54f0077509 target-s390x: implement TRANSLATE AND TEST instruction
It is part of the basic zArchitecture instructions. Allow it to be call
from EXECUTE.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-05 01:37:59 +02:00
Aurelien Jarno ed0bcecec1 target-s390x: implement LOAD FP INTEGER instructions
This is needed to pass the gcc.c-torture/execute/ieee/20010114-2.c test
in the gcc testsuite.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-05 01:37:59 +02:00
Aurelien Jarno 9182886d79 target-s390x: move SET DFP ROUNDING MODE to the correct facility
It belongs to the DFP rounding facility.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-05 01:37:59 +02:00
Aurelien Jarno f7c2114067 target-s390x: move STORE CLOCK FAST to the correct facility
STORE CLOCK FAST should be in the SCF facility.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-05 01:37:58 +02:00
Aurelien Jarno 74266b4a58 target-s390x: change CHRL and CGHRL format to RIL-b
Change to match the PoP. In practice both format RIL-a and RIL-b have
the same fields. They differ on the way we decode the fields, and it's
done correctly in QEMU.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-05 01:37:58 +02:00
Aurelien Jarno 1dedb9b76f target-s390x: fix CLGIT instruction
The COMPARE LOGICAL IMMEDIATE AND TRAP instruction should compare the
numbers as unsigned, as its name implies.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-05 01:37:58 +02:00
Aurelien Jarno a1c7610a68 target-s390x: implement LAY and LAEY instructions
This complete the general-instructions-extension facility, enable it.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
[agraf: remove facility bit]
Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-05 01:37:58 +02:00
Aurelien Jarno 92892330e7 target-s390x: move a few instructions to the correct facility
LY is part of the long-displacement facility.
RISBHG and RISBLG are part of the high-word facility.
STCMH is part of the z/Architecture.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
2015-06-05 01:37:58 +02:00
Alexander Graf 57af7289f2 s390x: Add interlocked access facility 1 instructions
We're currently missing all instructions defined by the "interlocked-access
facility 1" which is part of zEC12. This patch implements all of them except
for LPD and LPDG.

Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2015-05-13 14:48:54 +02:00
Alexander Graf 13f67dd582 s390x: Add some documentation in opcode list
I find it really hard to grasp what each field in the opcode list means.
Slowly walking through its semantics myself, I figured I'd write a small
summary at the top of the file to make life easier for me and whoever
looks at the file next.

Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2015-05-13 14:48:54 +02:00
Richard Henderson 0774710f1b target-s390: Implement ECAG
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-02-03 12:06:37 -08:00
Richard Henderson 9c3fd85b14 target-s390: Implement LURA, LURAG, STURG
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-02-03 12:06:37 -08:00
Richard Henderson e30a9d3fea target-s390: Implement EPSW
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-02-03 12:06:37 -08:00
Richard Henderson 8612c93583 target-s390: Implement SAM specification exception
Also, these are user-mode instructions; allow their use
in CONFIG_USER_ONLY.

Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-02-03 12:06:37 -08:00
Alexander Graf 44dd33ba8f s390x: Implement SAM{24,31,64}
The SAM instructions simply change 2 bits in PSW.MASK to advertise
the current memory mode. While we can't fully guarantee that 31 bit
mode (or even remotely 24 bit mode) actually work correctly, we don't
check whether lpswe modifies these bits, so we shouldn't keep the
guest from executing SAM instructions either.

This patch implements all SAM instrutions with their actual PSW changing
semantics, making more recent Linux kernels boot properly which do issue
a SAM31 call during early boot.

Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-11-05 12:01:28 +01:00
Richard Henderson b7886de3f3 target-s390: Perform COMPARE AND SWAP inline
Still no proper solution for CONFIG_USER_ONLY, but the system
version is significantly better.

Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-01-05 12:18:46 -08:00
Richard Henderson d074ac6d26 target-s390: Optimize XC
Notice XC with same address and convert that to store of zero.

Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-01-05 12:18:45 -08:00
Richard Henderson 411edc22cb target-s390: Implement LOAD/SET FP AND SIGNAL
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-01-05 12:18:45 -08:00
Richard Henderson a12000b9ec target-s390: Implement SET ROUNDING MODE
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-01-05 12:18:45 -08:00
Richard Henderson 1d1f630135 target-s390: Implement LCDFR
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-01-05 12:18:45 -08:00
Richard Henderson 2db014b5a7 target-s390: Implement CPSDR
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-01-05 12:18:45 -08:00
Richard Henderson 99b4f24b3e target-s390: Implement POPCNT
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-01-05 12:18:45 -08:00
Richard Henderson 2112bf1bfb target-s390: Implement CONVERT FROM LOGICAL
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-01-05 12:18:44 -08:00
Richard Henderson 6ac1b45f9b target-s390: Implement CONVERT TO LOGICAL
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-01-05 12:18:44 -08:00
Richard Henderson b92fa33486 target-s390: Implement STORE ON CONDITION
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-01-05 12:18:44 -08:00
Richard Henderson 632086da28 target-s390: Implement LOAD ON CONDITION
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-01-05 12:18:44 -08:00
Richard Henderson 1c26875182 target-s390: Implement COMPARE AND TRAP
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-01-05 12:18:44 -08:00
Richard Henderson 403e217f40 target-s390: Implement COMPARE RELATIVE LONG
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-01-05 12:18:44 -08:00
Richard Henderson e0def9094e target-s390: Implement PREFETCH
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-01-05 12:18:44 -08:00
Richard Henderson d6c6372e18 target-s390: Implement R[NOX]SBG
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-01-05 12:18:44 -08:00
Richard Henderson 143cbbc5eb target-s390: Implement LDGR, LGDR
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-01-05 12:18:44 -08:00
Richard Henderson 2d6a869833 target-s390: Implement RISBG
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-01-05 12:18:44 -08:00
Richard Henderson 5550359f07 target-s390: Implement COMPARE AND BRANCH
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-01-05 12:18:44 -08:00
Richard Henderson 2cf5e350c4 target-s390: Implement BRANCH ON INDEX
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-01-05 12:18:44 -08:00
Richard Henderson dc458df91d target-s390: Convert SERVC
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-01-05 12:18:43 -08:00
Richard Henderson 7ab938d706 target-s390: Convert LPSWE
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-01-05 12:18:43 -08:00
Richard Henderson fc778b55a5 target-s390: Convert STFL
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-01-05 12:18:43 -08:00
Richard Henderson d14b3e09b2 target-s390: Convert STSI
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-01-05 12:18:43 -08:00
Richard Henderson 14244b21a0 target-s390: Convert SACF
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-01-05 12:18:43 -08:00
Richard Henderson 39a5003c89 target-s390: Convert STCKE
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-01-05 12:18:43 -08:00
Richard Henderson 3d596f4912 target-s390: Convert CSP
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-01-05 12:18:43 -08:00
Richard Henderson 204504e2fa target-s390: Convert STURA
Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-01-05 12:18:43 -08:00
Richard Henderson 2c423fc070 target-s390: Convert subchannel instructions
While we're at it, list all of the chapter 14 subchannel insns.
Which is easy since all merely need indicate non-operation.

Signed-off-by: Richard Henderson <rth@twiddle.net>
2013-01-05 12:18:43 -08:00