Commit Graph

18 Commits

Author SHA1 Message Date
Alex Bennée
24f91e81b6 target/*/cpu.h: remove softfloat.h
As cpu.h is another typically widely included file which doesn't need
full access to the softfloat API we can remove the includes from here
as well. Where they do need types it's typically for float_status and
the rounding modes so we move that to softfloat-types.h as well.

As a result of not having softfloat in every cpu.h call we now need to
add it to various helpers that do need the full softfloat.h
definitions.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
[For PPC parts]
Acked-by: David Gibson <david@gibson.dropbear.id.au>
2018-02-21 10:20:24 +00:00
Richard Henderson
eed142195c target/hppa: Implement PROBE for system mode
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-31 05:30:50 -08:00
Helge Deller
6210db057a target/hppa: Implement halt and reset instructions
Real hardware would use an external device to control the power.
But for the moment let's invent instructions in reserved space,
to be used by our custom firmware.

Signed-off-by: Helge Deller <deller@gmx.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-31 05:30:49 -08:00
Richard Henderson
2dfcca9ffc target/hppa: Implement LPA
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30 10:22:26 -08:00
Richard Henderson
49c29d6c2e target/hppa: Implement the interval timer
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30 10:22:26 -08:00
Richard Henderson
c301f34e79 target/hppa: Implement IASQ
Any one TB will have only one space value.  If we change spaces,
we change TBs.  Thus BE and BEV must exit the TB immediately.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30 10:08:18 -08:00
Richard Henderson
f49b3537cb target/hppa: Implement rfi
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30 10:08:18 -08:00
Richard Henderson
e1b5a5ed6f target/hppa: Implement the system mask instructions
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30 10:08:18 -08:00
Richard Henderson
eaa3783b68 target/hppa: Split address size from register size
For system mode, we will need 64-bit virtual addresses even when
we have 32-bit register sizes.  Since the rest of QEMU equates
TARGET_LONG_BITS with the address size, redefine everything
related to register size in terms of a new TARGET_REGISTER_BITS.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30 10:08:18 -08:00
Richard Henderson
2986721df7 target/hppa: Define hardware exception types
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30 10:08:18 -08:00
Helge Deller
813dff13bf target/hppa: Skeleton support for hppa-softmmu
With the addition of default-configs/hppa-softmmu.mak, this
will compile.  It is not enabled with this patch, however.

Signed-off-by: Helge Deller <deller@gmx.de>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-01-30 10:08:18 -08:00
Laurent Vivier
98670d47cd accel/tcg: add size paremeter in tlb_fill()
The MC68040 MMU provides the size of the access that
triggers the page fault.

This size is set in the Special Status Word which
is written in the stack frame of the access fault
exception.

So we need the size in m68k_cpu_unassigned_access() and
m68k_cpu_handle_mmu_fault().

To be able to do that, this patch modifies the prototype of
handle_mmu_fault handler, tlb_fill() and probe_write().
do_unassigned_access() already includes a size parameter.

This patch also updates handle_mmu_fault handlers and
tlb_fill() of all targets (only parameter, no code change).

Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: David Hildenbrand <david@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20180118193846.24953-2-laurent@vivier.eu>
2018-01-25 16:02:24 +01:00
Emilio G. Cota
f9f46db444 target/hppa: check CF_PARALLEL instead of parallel_cpus
Thereby decoupling the resulting translated code from the current state
of the system.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Emilio G. Cota <cota@braap.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2017-10-24 13:53:41 -07:00
Richard Henderson
ebe9383cae target-hppa: Implement floating-point insns
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-23 09:52:40 -08:00
Richard Henderson
98a9cb792c target-hppa: Implement system and memory-management insns
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-23 09:52:40 -08:00
Richard Henderson
96d6407f36 target-hppa: Implement loads and stores
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-23 09:52:40 -08:00
Richard Henderson
b2167459ae target-hppa: Implement basic arithmetic
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-23 09:52:40 -08:00
Richard Henderson
61766fe9e2 target-hppa: Add framework and enable compilation
This is just about the minimum required to enable compilation
without actually executing any instructions.  This contains the
HPPACPU structure and the required callbacks, the gdbstub, the
basic translation loop, and a translate_one function that always
results in an illegal instruction.

Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-23 09:52:40 -08:00