Commit Graph

31 Commits

Author SHA1 Message Date
Aurelien Jarno
170d5b4bb9 target-i386: fix dpps and dppd SSE2 instructions
The helpers implemented dpps and dppd SSE instructions are not passing
the correct argument types to the softfloat functions. While they do
work anyway providing a correct behaviour, this patch fixes that.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-01-11 09:55:28 +01:00
Aurelien Jarno
adc7166611 target-i386: fix round{pd,ps,sd,ss} SSE2 instructions
roundps and roundss SSE2 instructions have been broken when switching
target-i386 to softfloat. They use float64_round_to_int to convert a
float32, and while the implicit conversion from float32 to float64 was
correct for softfloat-native, it is not for pure softfloat. Fix that by
using the correct registers and correct functions.

Also fix roundpd and roundsd implementation at the same time, even if
these functions are behaving correctly.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-01-11 09:55:28 +01:00
Aurelien Jarno
a4d1f14254 target-i386: fix {min,max}{pd,ps,sd,ss} SSE2 instructions
minpd, minps, minsd, minss and maxpd, maxps, maxsd, maxss SSE2
instructions have been broken when switching target-i386 to softfloat.
It's not possible to use comparison instructions on float types anymore
to softfloat, so use the floatXX_lt function instead, as the
float_XX_min and float_XX_max functions can't be used due to the Intel
specific behaviour.

As it implements the correct NaNs behaviour, let's remove the
corresponding entry from the TODO.

It fixes GDM screen display on Debian Lenny.

Thanks to Peter Maydell and Jason Wessel for their analysis of the
problem.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-01-11 09:55:28 +01:00
Blue Swirl
bc4268998d x86: fix pcmpestrm and pcmpistrm
Fix obvious typos (decrement and off-by-one error) in pcmpestrm and pcmpistrm
which resulted in infinite loop. Reported by Frank Mehnert,
spotted also by Coverity (bug 84752853).

Reported-by: Frank Mehnert <frank.mehnert@oracle.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-11-19 13:51:27 +00:00
Max Reitz
5c6562c204 target-i386: Fix several SSE3 instructions.
haddp[sd], hsubp[sd] and addsubp[sd] operate on floats, thus it is
necessary to use the appropriate floating point calculation functions.
If this is not done, those functions operate merely on integers, which
is not correct.

Signed-off-by: Max Reitz <max@tyndur.org>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-17 17:13:31 +00:00
Aurelien Jarno
c2ef9a83be target-i386: replace approx_rsqrt and approx_rcp by softfloat ops
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-25 11:18:33 +02:00
Aurelien Jarno
211315fb5e softfloat: rename float*_eq() into float*_eq_quiet()
float*_eq functions have a different semantics than other comparison
functions. Fix that by first renaming float*_quiet() into float*_eq_quiet().

Note that it is purely mechanical, and the behaviour should be unchanged.
That said it clearly highlight problems due to this different semantics,
they are fixed later in this patch series.

Cc: Alexander Graf <agraf@suse.de>
Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-17 20:32:14 +02:00
Aurelien Jarno
e0b29ce1cf target-i386: fix CMPUNORDPS/D and CMPORDPS/D instructions
SSE instructions CMPUNORDPS/D and CMPORDPS/D do not trigger an invalid
exception if operands are qNANs.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-17 20:32:14 +02:00
Andre Przywara
d9f4bb27db target-i386: add SSE4a instruction support
This adds support for the AMD Phenom/Barcelona's SSE4a instructions.
Those include insertq and extrq, which are doing shift and mask on
XMM registers, in two versions (immediate shift/length values and
stored in another XMM register).
Additionally it implements movntss, movntsd, which are scalar
non-temporal stores (avoiding cache trashing). These are implemented
as normal stores, though.
SSE4a is guarded by the SSE4A CPUID bit (Fn8000_0001:ECX[6]).

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-04 14:09:41 +02:00
Blue Swirl
1e6eec8b33 Fix Sparse warnings: add "static"
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-09-05 10:14:07 +00:00
Blue Swirl
8167ee8839 Update to a hopefully more future proof FSF address
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-07-16 20:47:01 +00:00
Blue Swirl
001faf3269 Replace gcc variadic macro extension with C99 version
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-05-13 17:53:17 +00:00
aurel32
fad6cb1a56 Update FSF address in GPL/LGPL boilerplate
The attached patch updates the FSF address in the GPL/LGPL boilerplate
in most GPL/LGPLed files, and also in COPYING.LIB.

Signed-off-by: Stuart Brady <stuart.brady@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6162 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-04 22:05:52 +00:00
aurel32
db8d990204 Remove FORCE_RET() and RETURN()
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5923 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07 18:15:54 +00:00
balrog
dcfd12b83e Fix pmovsx* / pmovzx* SSE instructions (original fix by Frank Mehnert).
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5841 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-01 01:52:37 +00:00
aurel32
30913bae9a target-i386: fix helper_pmovmskb_mmx helper
(malc)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5728 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-16 19:15:15 +00:00
balrog
000cacf6f9 Fix crc32w decoding, fix a constant width in blendvpd.
Forced the constant's width to long long so that it doesn't overflow,
problem spotted by C. W. Betts.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5417 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-04 11:33:52 +00:00
balrog
222a3336ec Implement SSE4.1, SSE4.2 (x86).
This adds support for CPUID_EXT_SSE41, CPUID_EXT_SSE42, CPUID_EXT_POPCNT
extensions.  Most instructions haven't been tested yet.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5411 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-04 03:27:44 +00:00
balrog
4242b1bd8a Implement x86 SSSE3 instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5315 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-25 18:01:46 +00:00
bellard
b8b6a50b55 converted more helpers to TCG - fixed some SVM issues
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4459 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-15 16:46:30 +00:00
bellard
5af451868c converted SSE/MMX ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4441 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-12 16:47:36 +00:00
aurel32
a35f3ec76b 3DNow! instruction set emulation
(Michael Tross)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4180 c046a42c-6fe2-441c-8c8c-71466251a162
2008-04-08 19:51:29 +00:00
ths
3b46e62427 find -type f | xargs sed -i 's/[\t ]*$//g' # Yes, again. Note the star in the regex.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3177 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-17 08:09:54 +00:00
ths
5fafdf24ef find -type f | xargs sed -i 's/[\t ]$//g' # on most files
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3173 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-16 21:08:06 +00:00
bellard
dabd98ddf5 fixed movd mmx/sse insn
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2321 c046a42c-6fe2-441c-8c8c-71466251a162
2007-01-16 19:28:58 +00:00
bellard
43fb823b5f removed switches in op.c (Paul Brook)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1400 c046a42c-6fe2-441c-8c8c-71466251a162
2005-04-26 20:38:17 +00:00
bellard
8422b11337 NaN support in FPU comparisons
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1341 c046a42c-6fe2-441c-8c8c-71466251a162
2005-03-20 10:39:24 +00:00
bellard
7a0e1f41ce soft float support
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1336 c046a42c-6fe2-441c-8c8c-71466251a162
2005-03-13 17:01:47 +00:00
bellard
0523c6b7c5 FORCE_RET() fixes - fpu fixes
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1236 c046a42c-6fe2-441c-8c8c-71466251a162
2005-01-23 20:46:31 +00:00
bellard
d52cf7a64a sse fix
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1224 c046a42c-6fe2-441c-8c8c-71466251a162
2005-01-16 01:07:28 +00:00
bellard
664e0f195a MMX/SSE support
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1205 c046a42c-6fe2-441c-8c8c-71466251a162
2005-01-08 18:58:29 +00:00