OpenE2K/qemu-e2k
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15 Commits

Author SHA1 Message Date
Paolo Bonzini
49a945a3c0 kill regs_to_env and env_to_regs 
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
 2010-01-19 16:31:02 -06:00
Blue Swirl
636aa20056 Replace always_inline with inline 
We define inline as always_inline.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
 2009-08-16 09:06:54 +00:00
Blue Swirl
8167ee8839 Update to a hopefully more future proof FSF address 
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
 2009-07-16 20:47:01 +00:00
aliguori
6a4955a813 qemu: per-arch cpu_has_work (Marcelo Tosatti) 
Blue Swirl: fix Sparc32 breakage

Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7238 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-04-24 18:03:20 +00:00
aurel32
fad6cb1a56 Update FSF address in GPL/LGPL boilerplate 
The attached patch updates the FSF address in the GPL/LGPL boilerplate
in most GPL/LGPLed files, and also in COPYING.LIB.

Signed-off-by: Stuart Brady <stuart.brady@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6162 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-01-04 22:05:52 +00:00
aurel32
9587035602 target-alpha: fix 2 warnings 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5992 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-11 22:42:42 +00:00
aurel32
8bb6e981e0 target-alpha: convert palcode ops to TCG 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5360 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-30 06:45:44 +00:00
aurel32
f18cd2238d target-alpha: convert FP ops to TCG 
- Convert FP ops to TCG
- Fix S format
- Implement F and G formats (untested)
- Fix MF_FPCR an MT_FPCR
- Fix FTOIS, FTOIT, ITOFF, ITOFS, ITOFT
- Fix CPYSN, CPYSE

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5354 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-29 17:21:28 +00:00
aurel32
04acd30726 target-alpha: convert remaining arith3 functions to TCG 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5254 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-18 13:45:14 +00:00
blueswir1
79383c9c08 Fix some warnings that would be generated by gcc -Wredundant-decls 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5115 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-30 09:51:20 +00:00
j_mayer
f071b4d3ca Alpha coding style and inlining fixes. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3462 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-10-28 00:56:24 +00:00
j_mayer
6ebbf39000 Replace is_user variable with mmu_idx in softmmu core, 
allowing support of more than 2 mmu access modes.
Add backward compatibility is_user variable in targets code when needed.
Implement per target cpu_mmu_index function, avoiding duplicated code
  and #ifdef TARGET_xxx in softmmu core functions.
Implement per target mmu modes definitions. As an example, add PowerPC
  hypervisor mode definition and Alpha executive and kernel modes definitions.
Optimize PowerPC case, precomputing mmu_idx when MSR register changes
  and using the same definition in code translation code.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3384 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-10-14 07:07:08 +00:00
ths
5fafdf24ef find -type f | xargs sed -i 's/[\t ]$//g' # on most files 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3173 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-09-16 21:08:06 +00:00
ths
bfed01fc79 Clean up of some target specifics in exec.c/cpu-exec.c. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2936 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-06-03 17:44:37 +00:00
j_mayer
4c9649a967 Alpha architecture emulation core. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2597 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-04-05 06:58:33 +00:00