Commit Graph

19853 Commits

Author SHA1 Message Date
Andreas Färber
d0e71ef56f target-microblaze: QOM'ify CPU init
Move code from cpu_mb_init() to a QOM initfn.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Tested-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
[AF: Leave cpu_reset() call in cpu_mb_init()]
2012-04-24 16:04:56 +02:00
Andreas Färber
61b6208f8e target-microblaze: QOM'ify CPU reset
Move code from cpu_state_reset() to QOM mb_cpu_reset().

Signed-off-by: Andreas Färber <afaerber@suse.de>
Tested-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
2012-04-24 16:04:56 +02:00
Andreas Färber
b77f98cada target-microblaze: QOM'ify CPU
Embed CPUMBState as first member of QOM MicroBlazeCPU.

Let CPUClass::reset() call cpu_state_reset() for now.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Tested-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
[AF: Updated cpu.c to include cpu-qom.h indirectly via cpu.h]
2012-04-24 16:04:56 +02:00
Andreas Färber
aa0d1267b3 target-cris: Start QOM'ifying CPU init
Move VR-independent code from cpu_cris_init() into an initfn.

Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-04-24 16:04:56 +02:00
Andreas Färber
1c3b52fb1a target-cris: QOM'ify CPU reset
Move code from cpu_state_reset() into QOM cris_cpu_reset().
Let CPU init call cpu_reset().

Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-04-24 16:04:56 +02:00
Andreas Färber
e739a48e58 target-cris: QOM'ify CPU
Embed CPUCRISState as first member of QOM CRISCPU.

Let CPUClass::reset() call cpu_state_reset() for now.

Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-04-24 16:04:56 +02:00
Anthony Liguori
092dfc7714 Merge remote-tracking branch 'origin/master' into staging
* origin/master:
  qtest: fix memread and memwrite on 32 bit hosts
2012-04-23 15:02:53 -05:00
Anthony Liguori
6454678423 Merge remote-tracking branch 'qmp/queue/qmp' into staging
* qmp/queue/qmp:
  qapi: g_hash_table_find() instead of GHashTableIter.
  qmp: make block job command naming consistent
2012-04-23 14:29:11 -05:00
Blue Swirl
ce6bf17a97 qtest: fix memread and memwrite on 32 bit hosts
Use PRIx64 to print 64 bit values to avoid truncation
on 32 bit hosts.

Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-04-23 19:28:14 +00:00
Anthony Liguori
1f8bcac09a Merge remote-tracking branch 'kwolf/for-anthony' into staging
* kwolf/for-anthony: (38 commits)
  qemu-iotests: Fix test 031 for qcow2 v3 support
  qemu-iotests: Add -o and make v3 the default for qcow2
  qcow2: Zero write support
  qemu-iotests: Test backing file COW with zero clusters
  qemu-iotests: add a simple test for write_zeroes
  qcow2: Support for feature table header extension
  qcow2: Support reading zero clusters
  qcow2: Version 3 images
  qcow2: Ignore reserved bits in check_refcounts
  qcow2: Ignore reserved bits in refcount table entries
  qcow2: Simplify count_cow_clusters
  qcow2: Refactor qcow2_free_any_clusters
  qcow2: Ignore reserved bits in L1/L2 entries
  qcow2: Fail write_compressed when overwriting data
  qcow2: Ignore reserved bits in count_contiguous_clusters()
  qcow2: Ignore reserved bits in get_cluster_offset
  qcow2: Save disk size in snapshot header
  Specification for qcow2 version 3
  qcow2: Fix refcount block allocation during qcow2_alloc_cluster_at()
  iotests: Resolve test failures caused by hostname
  ...
2012-04-23 14:27:04 -05:00
Anthony Liguori
cb4c2548ea Merge remote-tracking branch 'origin/master' into staging
* origin/master:
  fix BCD mask for date (Solaris 2.5 guest hang fix)
2012-04-23 14:15:09 -05:00
Artyom Tarasenko
02f5da11d6 fix BCD mask for date (Solaris 2.5 guest hang fix)
Fix BCD mask for date. The most visible effect of this patch is
Solaris 2.5.1 doesn't hang at boot if the day of month is >21.

Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-04-23 17:01:04 +00:00
Anthony Liguori
5469963394 Merge remote-tracking branch 'origin/master' into staging
* origin/master: (27 commits)
  target-arm: Move reset handling to arm_cpu_reset
  target-arm: Drop cpu_reset_model_id()
  target-arm: Move cache ID register setup to cpu specific init fns
  target-arm: Move OMAP cp15_i_{max,min} reset to cpu_state_reset
  target-arm: Move feature register setup to per-CPU init fns
  target-arm: Move iWMMXT wCID reset to cpu_state_reset
  target-arm: Drop JTAG_ID documentation
  target-arm: Move SCTLR reset value setup to per cpu init fns
  target-arm: Move CTR setup to per cpu init fns
  target-arm: Move MVFR* setup to per cpu init fns
  target-arm: Move FPSID config to cpu init fns
  target-arm: Move feature bit settings to CPU init fns
  target-arm: Add QOM subclasses for each ARM cpu implementation
  target-arm: remind to keep arm features in sync with linux-user/elfload.c
  tci: GETPC() macro must return an uintptr_t
  gdbstub: Synchronize CPU state unconditionally in gdb_set_cpu_pc
  softfloat: make USE_SOFTFLOAT_STRUCT_TYPES compile
  target-xtensa: add tests for LOOPNEZ and LOOPGTZ
  target-xtensa: fix LOOPNEZ/LOOPGTZ translation
  qtest: add m48t59 tests for Sparc
  ...
2012-04-23 11:49:59 -05:00
NODA, Kai
57a33d8967 qapi: g_hash_table_find() instead of GHashTableIter.
GHashTableIter was first introduced in glib 2.16.
This patch removes it in favor of older g_hash_table_find()
for better compatibility with RHEL5.

Signed-off-by: NODA, Kai <nodakai@gmail.com>
Signed-off-by: Luiz Capitulino <lcapitulino@redhat.com>
2012-04-23 13:03:45 -03:00
Stefan Hajnoczi
db58f9c060 qmp: make block job command naming consistent
The block streaming and job commands used '_' instead of '-' for reasons
of compatibility with libvirt, which already included support for the
'_' naming.  However, the semantics of block_job_cancel have changed and
libvirt now needs to handle the new semantics.

Since the old semantics were never in a QEMU release we can still rename
the commands to use '-' instead of '_'.  Libvirt is also happy because
the new name can be used to distinguish QEMU binaries that support the
latest block-job-cancel semantics from those that include a downstream
block_job_cancel command.

Therefore, let's apply the QAPI/QMP naming rules to the block streaming
and job commands.  QEMU 1.1 will be the first release with these
commands so no upstream users can break.

Note that HMP commands are left with '_' because that is the convention
there.

Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Luiz Capitulino <lcapitulino@redhat.com>
2012-04-23 13:02:01 -03:00
Anthony Liguori
53878a132a Merge remote-tracking branch 'sstabellini/build_fix' into staging
* sstabellini/build_fix:
  xen: add a dummy xc_hvm_inject_msi for Xen < 4.2
  xen,configure: detect Xen 4.2
2012-04-23 09:58:54 -05:00
Anthony Liguori
6b03296606 Merge remote-tracking branch 'stefanha/trivial-patches' into staging
* stefanha/trivial-patches:
  Add .gitignore for tests/
  e1000: Fix spelling (segmentaion -> segmentation) in debug output
  spice-qemu-char.c: Show what name is unsupported
  pflash_cfi01: remove redundant line
  qxl: Add missing GCC_FMT_ATTR and fix format specifier
  fix block_job_set_speed name in documentation
  error.c: don't return value for void function
2012-04-23 09:58:33 -05:00
Anthony Liguori
25896d8063 Merge remote-tracking branch 'mdroth/qga-pull-4-19-12' into staging
* mdroth/qga-pull-4-19-12:
  qemu-ga: fix help output
  qemu-ga: generate missing stubs for fsfreeze
2012-04-23 09:58:19 -05:00
Anthony Liguori
bec8eb8136 Merge remote-tracking branch 'bonzini/nbd-next' into staging
* bonzini/nbd-next:
  nbd: obey FUA on reads
  nbd: do not include block_int.h
  nbd: do not block in nbd_wr_sync if no data at all is available
  nbd: consistently return negative errno values
  nbd: consistently check for <0 or >=0
  nbd: consistently use ssize_t
  nbd: avoid out of bounds access to recv_coroutine array
2012-04-23 09:58:01 -05:00
Anthony Liguori
4a1873fc8c Merge remote-tracking branch 'bonzini/scsi-next' into staging
* bonzini/scsi-next:
  scsi: add SANITIZE command
  SCSI emulation: should tell the guest that we actually support thin provisioning
  SCSI emulation: Support unmap via WRITE_SAME_10.
  scsi: advertise DPOFUA
  scsi: small refactoring of MMC mode-sense
  scsi: support FUA on reads
  scsi: add a started field to SCSIDiskReq
  scsi: force unit access on VERIFY
  scsi: add support for FUA on writes
  scsi: move scsi_flush_complete around
  scsi: make code more homogeneous in AIO callback functions
  scsi: add missing test for cancelled request
  virtio-scsi: add multiqueue capability
  virtio: add virtio_queue_get_id
  virtio-scsi: prepare migration format for multiqueue
  scsi: fix memory leak
2012-04-23 09:57:47 -05:00
Anthony Liguori
e5e3895702 Merge remote-tracking branch 'stefanha/tracing' into staging
* stefanha/tracing:
  tracetool: handle DTrace keywords 'in', 'next', 'self'
  tracetool: Add MAINTAINERS info
  tracetool: Add support for the 'dtrace' backend
  tracetool: Add support for the 'ust' backend
  tracetool: Add support for the 'simple' backend
  tracetool: Add support for the 'stderr' backend
  tracetool: Add module for the 'h' format
  tracetool: Add module for the 'c' format
  tracetool: Rewrite infrastructure as python modules
2012-04-23 09:57:04 -05:00
Peter Maydell
3c30dd5a68 target-arm: Move reset handling to arm_cpu_reset
Now that cpu_reset_model_id() has gone we can move the
reset code over to the class reset function and have cpu_state_reset
simply do a reset on the CPU QOM object.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Andreas Färber <afaerber@suse.de>
2012-04-21 18:13:22 +00:00
Peter Maydell
caa1d0779e target-arm: Drop cpu_reset_model_id()
cpu_reset_model_id() is now empty and we can remove it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Andreas Färber <afaerber@suse.de>
2012-04-21 18:13:19 +00:00
Peter Maydell
85df3786b2 target-arm: Move cache ID register setup to cpu specific init fns
Move cache ID register reset out of cpu_reset_model_id() by
creating a field for the reset value in ARMCPU and setting it
up in the cpu specific init functions.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Andreas Färber <afaerber@suse.de>
2012-04-21 18:12:29 +00:00
Peter Maydell
8092d2f031 target-arm: Move OMAP cp15_i_{max,min} reset to cpu_state_reset
Move the OMAP-specific cp15_i_{max,min} reset to cpu_state_reset;
since these registers are only accessible on CPUs with the
OMAPCP feature set there's no need to guard this reset with
either a CPUID or feature bit check.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andreas Färber <afaerber@suse.de>
2012-04-21 18:12:27 +00:00
Peter Maydell
2e4d7e3e3e target-arm: Move feature register setup to per-CPU init fns
Move feature register value setup to per-CPU init functions.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Andreas Färber <afaerber@suse.de>
2012-04-21 18:11:38 +00:00
Peter Maydell
0cc892fd97 target-arm: Move iWMMXT wCID reset to cpu_state_reset
Move the iWMMXT wCID reset to cpu_state_reset(). Since
we use the same value for all CPUs with this feature
(with the major/minor revision fields set to the QEMU
specific 'Q' value) there's no need to create an ARMCPU
field just for this.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andreas Färber <afaerber@suse.de>
2012-04-21 18:11:35 +00:00
Peter Maydell
4e851c380e target-arm: Drop JTAG_ID documentation
None of the machines in QEMU offer a JTAG debug interface, so this info
was unused. Further, the PXA250 ID contradicts the February 2002
Developer's Manual, which has it as 0xn9264013 with n the MIDR Revision.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-21 18:11:32 +00:00
Peter Maydell
0ca7e01cbc target-arm: Move SCTLR reset value setup to per cpu init fns
Move the reset value of SCTLR to ARMCPU, initialised in
the per-cpu init functions. It can then be reset by a
simple copy, and we can drop the code from cpu_reset_model_id().

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Andreas Färber <afaerber@suse.de>
2012-04-21 18:10:44 +00:00
Peter Maydell
64e1671fd4 target-arm: Move CTR setup to per cpu init fns
Move CTR (cache type register) value to an ARMCPU field
set up by per-cpu init fns.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Andreas Färber <afaerber@suse.de>
2012-04-21 18:09:53 +00:00
Peter Maydell
bd35c3553b target-arm: Move MVFR* setup to per cpu init fns
Move the MVFR* VFP feature register values to ARMCPU,
so they are set up by the implementation-specific instance
init functions rather than in cpu_reset_model_id().

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Andreas Färber <afaerber@suse.de>
2012-04-21 18:09:00 +00:00
Peter Maydell
325b3ceff6 target-arm: Move FPSID config to cpu init fns
Move the reset FPSID to the ARMCPU struct, and set it in the
per-implementation instance init function. At reset we then
just copy the reset value into the CPUARMState field.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Andreas Färber <afaerber@suse.de>
2012-04-21 18:08:12 +00:00
Peter Maydell
581be09434 target-arm: Move feature bit settings to CPU init fns
Move the setting of the feature bits from cpu_reset_model_id()
to each CPU's instance init function. This requires us to move
the features field in CPUARMState so that it is not cleared
on reset.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Andreas Färber <afaerber@suse.de>
2012-04-21 18:07:21 +00:00
Peter Maydell
777dc78411 target-arm: Add QOM subclasses for each ARM cpu implementation
Register subclasses for each ARM CPU implementation.

Let arm_cpu_list() enumerate CPU subclasses in alphabetical order,
except for special value "any".

Replace cpu_arm_find_by_name()'s string -> CPUID lookup by storing the
CPUID (aka MIDR, Main ID Register) value in the class.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-21 18:06:27 +00:00
Benoit Canet
ce854d7cc3 target-arm: remind to keep arm features in sync with linux-user/elfload.c
Signed-off-by: Benoit Canet <benoit.canet@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-21 18:04:51 +00:00
Blue Swirl
75f05e4fd7 Merge branch 'arm-devs.for-upstream' of git://git.linaro.org/people/pmaydell/qemu-arm
* 'arm-devs.for-upstream' of git://git.linaro.org/people/pmaydell/qemu-arm:
  versatiblepb: add NOR flash support
  hw/arm_mptimer: Reset the qemu_timer at reset
  versatilepb: add ds1338 rtc device
  realview: break out versatile i2c controller code
2012-04-21 13:33:55 +00:00
Stefan Weil
c3ca04679e tci: GETPC() macro must return an uintptr_t
Change the data type of tci_tb_ptr, so GETPC() returns an
uintptr_t now (like for all other TCG targets).

This completes commit 2050396801
and fixes builds with TCI.

Signed-off-by: Stefan Weil <sw@weilnetz.de>
Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-04-21 13:28:28 +00:00
Peter Maydell
a896d03bb5 gdbstub: Synchronize CPU state unconditionally in gdb_set_cpu_pc
Synchronize the CPU state via cpu_sychronize_state() unconditionally
in gdb_set_cpu_pc() rather than only in some of the target ifdef
ladder cases.

We can divide the CPUs into three categories:
 * non-KVM targets: no change of behaviour since we will use the
   kvm-stub.c no-op function.
 * i386 and s390: no change of behaviour since they were already
   calling this function
 * PPC (in KVM mode): this fixes an error: failing to synchronise
   was accidental and probably a bug.

This also paves the way for other targets (specifically ARM) which
can add KVM support in future without having to add another target
specific change to this bit of code.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-04-21 13:27:34 +00:00
Juan Quintela
0eb4fc817f softfloat: make USE_SOFTFLOAT_STRUCT_TYPES compile
This change makes it compile and return the same value than the #undef one.

Signed-off-by: Juan Quintela <quintela@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-04-21 13:26:47 +00:00
Max Filippov
536a98d4d6 target-xtensa: add tests for LOOPNEZ and LOOPGTZ
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-04-21 13:24:50 +00:00
Max Filippov
b18b37f7c5 target-xtensa: fix LOOPNEZ/LOOPGTZ translation
Translation of LOOP instructions used to call LEND SR write handler to
update LEND and invalidate relevant TBs. Now that LEND SR write handler
ends TB, LOOPNEZ and LOOPGTZ generate wrong code (same as for simple
LOOP). Fix it by calling wsr_lend helper directly.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-04-21 13:24:45 +00:00
Blue Swirl
f91837a7f1 qtest: add m48t59 tests for Sparc
Add simple m48t59 qtests, enable test only for Sparc32
and Sparc64. On PPC, the device is behind PCI bus.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-04-21 07:10:25 +00:00
Eric Benard
964c695a54 versatiblepb: add NOR flash support
- add support for the 64MB NOR CFI01 flash available at
0x34000000 on the versatilepb board
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0225d/BBAJIHEC.html

- tested with barebox bootloader

Signed-off-by: Eric Bénard <eric@eukrea.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-20 15:39:05 +00:00
Peter Maydell
bdac1c1e95 hw/arm_mptimer: Reset the qemu_timer at reset
On reset of the mpcore timer/watchdog block we need to
delete the qemu_timer in case it was running.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-20 15:38:52 +00:00
Oskar Andero
b1f05696cc versatilepb: add ds1338 rtc device
Add ds1338 rtc attached on i2c.

Signed-off-by: Oskar Andero <oskar.andero@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-20 15:38:52 +00:00
Oskar Andero
d1157ca418 realview: break out versatile i2c controller code
The versatile i2c controller implementation was separated to
its own file called versatile_i2c.c. This is done as a preparation
for adding i2c support to the versatilepb board.

Signed-off-by: Oskar Andero <oskar.andero@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-04-20 15:38:52 +00:00
Kevin Wolf
1042ec94b1 qemu-iotests: Fix test 031 for qcow2 v3 support
qcow2.py must be updated to work with version 3 images at all, the
output has changed since the feature table extension has been added, and
version 2 and version 3 images can't possibly have the same test output.

Change the test case to completely ignore IMGOPTS and run the test for
both compat=1.1 and compat=0.10 regardless of the ./check command line.

Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2012-04-20 15:57:30 +02:00
Kevin Wolf
8900436891 qemu-iotests: Add -o and make v3 the default for qcow2
This adds an -o option to qemu-iotests, which is an option string that
is passed through to qemu-img create -o... This allows testing different
subformat with a command like './check -qcow2 -o compat=0.10'.

For qcow2, if no compat option is specified, compat=1.1 is the new
default.

Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2012-04-20 15:57:30 +02:00
Kevin Wolf
621f058940 qcow2: Zero write support
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2012-04-20 15:57:30 +02:00
Kevin Wolf
ab3a32ad5e qemu-iotests: Test backing file COW with zero clusters
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2012-04-20 15:57:30 +02:00