Drop the #if 0'ed alternative to make it "ppc64" for TARGET_PPC64.
If we ever want to change it, we can more easily do so now.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
Move definitions that were 100% identical except for the name into a
list of aliases so that we don't register duplicate CPU types.
Drop the accompanying comments since they don't really add value.
We need to support recursive lookup due to code names referencing a
generic name referencing a specific model revision.
List aliases separately for -cpu ?.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
To repurpose the POWERPC_DEF_SVR() macro outside of an array,
move the comma into the macro. No functional change.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
It is within a large TARGET_PPC64 section from 970 to 620,
so an #endif /* TARGET_PPC64 */ is confusing. Clean this up.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
Commit fe828a4d4b added a new fatal error
message while QOM realize'ification was in flight.
Convert it to return an Error instead of exit()ing.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
Unlike derived PVR constants mapped to CPU_POWERPC_G2LEgp3, the
"G2leGP3" model definition itself used the CPU_POWERPC_G2LEgp1 PVR.
Fixing this will allow to alias CPU_POWERPC_G2LEgp3-using types to
"G2leGP3".
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
It was defined to ..._MPC8545E_v21 rather than ..._MPC8547E_v21.
Due to both resolving to CPU_POWERPC_e500v2_v21 this did not show.
Fixing this nontheless helps with QOM'ifying CPU aliases.
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
Currently the spapr-vlan device does not supply a cleanup call for its
NetClientInfo structure. With current qemu versions, that leads to a SEGV
on exit, when net_cleanup() attempts to call the cleanup handlers on all
net clients.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Alexander Graf <agraf@suse.de>
virtio-console.c used to return a value less than the number of bytes
asked to be written out to a chardev backend in case the backend is not
writable. virtio-serial-bus.c then implicitly enabled flow control for
that port.
Make this explicit instead.
Signed-off-by: Amit Shah <amit.shah@redhat.com>
Message-id: f5ec50b068c25422256e499cf4adc06d353bf394.1362505276.git.amit.shah@redhat.com
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
The virtio-serial-bus already has the logic to make flow control work
properly. Hook into the char layer's new ability to signal a backend is
writable again.
Signed-off-by: Amit Shah <amit.shah@redhat.com>
Message-id: abffa02235d55ca6e2489068c58971c8897e976c.1362505276.git.amit.shah@redhat.com
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This allows a front-end to request for a callback when the backend
is writable again.
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Signed-off-by: Amit Shah <amit.shah@redhat.com>
Message-id: 96f93c0f741064604bbb6389ce962191120af8b7.1362505276.git.amit.shah@redhat.com
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
I didn't bother switching to g_io_channel_read/write because we need to use
sendmsg on Unix. No problem though since we're using an unbuffered channel.
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Signed-off-by: Amit Shah <amit.shah@redhat.com>
Message-id: 002f726576dfb51bca4854aa257b74d77c1cd4e8.1362505276.git.amit.shah@redhat.com
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This is a special GSource that supports CharDriverState style
poll callbacks.
For reviewability and bisectability, this code is #if 0'd out in this
patch to avoid unused warnings since all of the functions are static.
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Signed-off-by: Amit Shah <amit.shah@redhat.com>
Message-id: 9b59ac17b9d0bb3972a73fed04d415f07b391936.1362505276.git.amit.shah@redhat.com
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This code is very old dating back to 2007. What is puzzling is that
STDIO_MAX_CLIENTS was always #define to 1 meaning that all of the code to deal
with more than one client was unreachable.
Just remove the whole mess of it.
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Signed-off-by: Amit Shah <amit.shah@redhat.com>
Message-id: d276bccdbf4e7463020c5f539f61ae3bfbc88d1d.1362505276.git.amit.shah@redhat.com
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Right now the inet connect code tries all available addresses but until one
doesn't fail. It passes local_err each time without clearing it from the
previous failure. This can trigger an assert since the inet connect code
tries to set an error on an object != NULL.
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Signed-off-by: Amit Shah <amit.shah@redhat.com>
Message-id: 16c806d60aa5e9660ed7751bb4e37dcd278f97f0.1362505276.git.amit.shah@redhat.com
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
The BIT6 of Status Register(SR):
SR[6] behaves the same as R/B# pin
SR[6] = 0 indicates the device is busy;
SR[6] = 1 means the device is ready
Some NAND flash controller (i.e. ftnandc021) relies on the SR[6]
to determine if the NAND flash erase/program is success or error timeout.
P.S:
The exmaple NAND flash datasheet could be found at following link:
http://www.mxic.com.tw/QuickPlace/hq/PageLibrary4825740B00298A3B.nsf/h_Index/8FEA549237D2F7674825795800104C26/$File/MX30LF1G08AA,%203V,%201Gb,%20v1.1.pdf
Signed-off-by: Kuo-Jung Su <dantesu@gmail.com>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
* 'target-arm.next' of git://git.linaro.org/people/pmaydell/qemu-arm:
MAINTAINERS: add entry for ARM KVM guest cores
configure: Enable KVM on ARM
hw/kvm/arm_gic: Implement support for KVM in-kernel ARM GIC
target-arm: Use MemoryListener to identify GIC base address for KVM
hw/arm_gic: Convert ARM GIC classes to use init/realize
hw/arm_gic: Add presave/postload hooks
ARM KVM: save and load VFP registers from kernel
ARM: KVM: Add support for KVM on ARM architecture
target-arm: Drop CPUARMState* argument from bank_number()
linux-headers: resync from mainline to add ARM KVM headers
oslib-posix: Align to permit transparent hugepages on ARM Linux
target-arm: Don't decode RFE or SRS on M profile cores
target-arm: Factor out handling of SRS instruction
N32 is a 64-bit cpu with a 32-bit address space. We have
existing cpp defines for this situation, but weren't using them.
This does mean that the linux-user/mipsn32 directory must be
merged with the linux-user/mips64 directory, and differences
must be resolved via ifdefs.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
