In one of the last commits we accidently got 3-space indentation into
the tree. Fix it up so it's 4 spaces wide.
Reported-by: Andreas Faerber <afaerber@suse.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
Add a CPU reset handler to have all CPUs in a PoP compliant
state.
Signed-off-by: Jens Freimann <jfrei@linux.vnet.ibm.com>
[agraf: move hw/hw.h into existing ifdef]
Signed-off-by: Alexander Graf <agraf@suse.de>
The function is only used in misc_helper.c, so move it to that file.
This reduces the size of debug executables (compiled without optimization)
because they get unused code and data for each compilation which includes
cpu.h.
Executables with optimization don't change their size.
ebcdic2ascii is currently unused and could be removed (not done here).
The array ascii2ebcdic must be accessed with an unsigned index, therefore
(int)ascii[i] was replaced by (uint8_t)ascii[i]. The old code would have
failed for a signed char less than 0. The current code only converts
"QEMU" and spaces to EBCDIC, so there is no problem today.
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
This enables qemu -cpu help to return a list of supported CPU models
on s390 and also to query for cpu definitions in the monitor.
Initially only cpu model = host is returned. This needs to be reworked
into a full-fledged CPU model handling later on.
This change is needed to allow libvirt exploiters (like OpenStack)
to specify a CPU model.
Signed-off-by: Viktor Mihajlovski <mihajlov@linux.vnet.ibm.com>
Signed-off-by: Jens Freimann <jfrei@linux.vnet.ibm.com>
Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com>
[agraf: fix s390x-linux-user, adjust header locations]
Signed-off-by: Alexander Graf <agraf@suse.de>
IBMs s390 contributions were meant to to be gplv2 or later (since
we were contributing to qemu). Several of the s390 specific files
link to gpl code anyway, so lets clarify the licence statement for
new contributions for those files that we have touched multiple
times or will likely touch again.
This patch does not touch files that mostly deal with tcg.
Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Note that target-alpha accesses this field from TCG, now using a
negative offset. Therefore the field is placed last in CPUState.
Pass PowerPCCPU to [kvm]ppc_fixup_cpu() to facilitate this change.
Move common parts of mips cpu_state_reset() to mips_cpu_reset().
Acked-by: Richard Henderson <rth@twiddle.net> (for alpha)
[AF: Rebased onto ppc CPU subclasses and openpic changes]
Signed-off-by: Andreas Färber <afaerber@suse.de>
The division routines do not read or write tcg registers,
but can raise fixed-point divide exceptions.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Don't load the displacement into a register first, add it second
so that tcg_gen_addi_i64 can eliminate zeros. Don't mask the
displacement first so that we don't turn small negative numbers
into large positive numbers.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Giving the proper mask to disas_jcc allows us to generate an inline
comparison generating the carry/borrow with setcond.
In the very worst case, when we must use the external helper to compute
a value for CC, we generate (cc > 1) instead of (cc >> 1), which is only
very slightly slower on common cpus.
In the very best case, when the CC comes from a COMPARE insn and the
compiler is using ALCG with zero, everything folds out to become just
the setcond that the compiler wanted.
Signed-off-by: Richard Henderson <rth@twiddle.net>
After full conversion, we can audit the uses of LTGT cc ops
and see that none of the instructions can ever set CC=3.
Thus we can extend the table to treat that bit as ignored.
This fixes a regression wrt the pre-conversion translation
in which NE was used for both m=6 and m=7.
Signed-off-by: Richard Henderson <rth@twiddle.net>
While they aren't expensive, they aren't free to process. When we
know that the three cc helper variables are dead, don't kill them.
Signed-off-by: Richard Henderson <rth@twiddle.net>
There's no need to force computation of the true cc_op when taking an
exception or single stepping. In either case we'll enter the next TB
with s->cc_op = DYNAMIC and recompute anyway. Just make sure that
s->cc_op is stored back to env->cc_op as needed.
Delete some dead functions, avoid allocating unused TCG temps, drop
the old s->is_jmp setting.
Signed-off-by: Richard Henderson <rth@twiddle.net>
The use of inline restricts detection of static functions that are
no longer used. Limit the use of inline to those functions that
are conditionally used based on CONFIG_USER_ONLY.
Signed-off-by: Richard Henderson <rth@twiddle.net>
While we're at it, list all of the chapter 14 subchannel insns.
Which is easy since all merely need indicate non-operation.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Note that truncating the store to r1 based on PSW_MASK_64
is incorrect. We always modify the entire register.
Signed-off-by: Richard Henderson <rth@twiddle.net>
The code that was in gen_op_mvc was a bit confused wrt what lengths
it wanted to handle. I also disbelieve that the inline memset is
worthwhile.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Change the CC handling to be more like TEST UNDER MASK, with val & mask.
This lets us handle ICMH much more like ICM.
Signed-off-by: Richard Henderson <rth@twiddle.net>
The inline markers hid the fact that {n}abs_32 were unused
because of typos in the main do_calc_cc function. Let the
compiler handle auto-inlining here.
Signed-off-by: Richard Henderson <rth@twiddle.net>
I'm resonably certain that the carry/borrow-out condition for both
helpers was incorrect, failing to take into account the carry-in.
Adding the new CC_OP codes also allows removing the awkward interface
we used for the slb helpers.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Use a new "retxl" member of CPUS290XState to return the "eXtra Low" part
of a 128-bit value. That said, this will get used when two independent
values need returning (e.g. quotient+remainder) as well.
At the same time, shuffle the elements of CPUS390XState to get this new
space from existing padding in the structure.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Make the user path more like the system path. Prepare for more kinds
of runtime exceptions. Rename ILC to ILEN to make it clear that we
want to pass around a full instruction length, rather than a "code"
that happens to be stored one bit left in a larger field.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Lots of duplicated code replaced with a couple of tables. We no longer
attempt to manually invert the logic operation: the comments now match
the code. In the fully general test, constant propagate (1 << (3 - cc))
into (8 >> cc).
The new function will be usable by non-branch insns as well.
Signed-off-by: Richard Henderson <rth@twiddle.net>
We were treating psw.mask as the 32-bit quantity it is in ESA mode.
In particular, the CC field was at the wrong place.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Yes, we're about to rewrite all of this, but having this unconditional
jump recompute cc_op is a large source of "false diff errors" when
trying to examine before and after dumps.
Signed-off-by: Richard Henderson <rth@twiddle.net>
DISAS_EXCP is exit via exception; we wanted DISAS_JUMP.
This matters when we start cleaning up the TB exit paths.
Signed-off-by: Richard Henderson <rth@twiddle.net>
At the same time, tidy other usages of tcg_gen_deposit_i64.
In some cases we can "type cast" rather than extend, and in
others we can allow tcg_gen_deposit_i64 itself to optimize
the HOST_LONG_BITS==32 case.
Signed-off-by: Richard Henderson <rth@twiddle.net>
