Commit Graph

128 Commits

Author SHA1 Message Date
Anthony Liguori 98c8a73b2e Merge remote-tracking branch 'afaerber/qom-cpu' into staging
* afaerber/qom-cpu: (35 commits)
  target-i386: Pass X86CPU to kvm_handle_halt()
  target-i386: Pass X86CPU to kvm_get_mp_state()
  cpu: Move thread_id to CPUState
  cpus: Pass CPUState to run_on_cpu()
  target-i386: Pass X86CPU to cpu_x86_inject_mce()
  target-i386: Pass X86CPU to kvm_mce_inject()
  cpus: Pass CPUState to [qemu_]cpu_has_work()
  spapr: Pass PowerPCCPU to hypercalls
  spapr: Pass PowerPCCPU to spapr_hypercall()
  target-ppc: Pass PowerPCCPU to cpu_ppc_hypercall
  target-ppc: Pass PowerPCCPU to powerpc_excp()
  xtensa_pic: Pass XtensaCPU to xtensa_ccompare_cb()
  cpus: Pass CPUState to qemu_wait_io_event_common()
  cpus: Pass CPUState to flush_queued_work()
  cpu: Move queued_work_{first,last} to CPUState
  cpus: Pass CPUState to qemu_cpu_kick()
  target-ppc: Rename kvm_kick_{env => cpu} and pass PowerPCCPU
  ppc: Pass PowerPCCPU to {ppc6xx,ppc970,power7,ppc40x,ppce500}_set_irq()
  cpus: Pass CPUState to qemu_tcg_init_vcpu()
  cpus: Pass CPUState to qemu_tcg_cpu_thread_fn
  ...

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-11-01 11:12:32 -05:00
Jia Liu 853c3240c0 target-mips: Add ASE DSP resources access check
Add MIPS ASE DSP resources access check.

Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31 20:24:06 +01:00
Andreas Färber 3993c6bddf cpus: Pass CPUState to [qemu_]cpu_has_work()
For target-mips also change the return type to bool.

Make include paths for cpu-qom.h consistent for alpha and unicore32.

Signed-off-by: Andreas Färber <afaerber@suse.de>
[AF: Updated new target-openrisc function accordingly]
Acked-by: Richard Henderson <rth@twiddle.net> (for alpha)
2012-10-31 04:11:37 +01:00
Avi Kivity a8170e5e97 Rename target_phys_addr_t to hwaddr
target_phys_addr_t is unwieldly, violates the C standard (_t suffixes are
reserved) and its purpose doesn't match the name (most target_phys_addr_t
addresses are not target specific).  Replace it with a finger-friendly,
standards conformant hwaddr.

Outstanding patchsets can be fixed up with the command

  git rebase -i --exec 'find -name "*.[ch]"
                        | xargs s/target_phys_addr_t/hwaddr/g' origin

Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-10-23 08:58:25 -05:00
Blue Swirl 895c2d0435 target-mips: switch to AREG0 free mode
Add an explicit CPUState parameter instead of relying on AREG0
and switch to AREG0 free mode.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Acked-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-15 17:51:13 +00:00
Maciej W. Rozycki 03e6e50177 MIPS/user: Fix reset CPU state initialization
This change updates the CPU reset sequence to use a common piece of code
that figures out CPU state flags, fixing the problem with MIPS_HFLAG_COP1X
not being set where applicable that causes floating-point MADD family
instructions (and other instructions from the MIPS IV FP subset) to trap.

 As compute_hflags is now shared between op_helper.c and translate.c, the
function is now moved to a common header.  There are no changes to this
function.

 The problem was seen with the 24Kf MIPS32r2 processor in user emulation.
The new approach prevents system and user emulation from diverging -- all
the hflags state is initialized in one place now.

Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-09-08 01:37:23 +02:00
Andreas Färber b7e516ce04 Kill off cpu_state_reset()
In commit 1bba0dc932 cpu_reset()
was renamed to cpu_state_reset(), to allow introducing a new cpu_reset()
that would operate on QOM objects.

All callers have been updated except for one in target-mips, so drop all
implementations except for the one in target-mips and move the
declaration there until MIPSCPU reset can be fully QOM'ified.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Michael Walle <michael@walle.cc> (for lm32)
Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa)
Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> (for mb + cris)
Acked-by: Alexander Graf <agraf@suse.de> (for ppc)
Acked-by: Blue Swirl <blauwirbel@gmail.com>
2012-06-04 23:00:45 +02:00
Andreas Färber 30bf942d8c target-mips: Let cpu_mips_init() return MIPSCPU
Turn cpu_init macro into a static inline function returning CPUMIPSState
for backwards compatibility.

Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-06-04 23:00:43 +02:00
Andreas Färber bed38e425f target-mips: Remove commented-out function declaration
There is no function cpu_mips_get_clock(), so drop it.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Stefan Weil <sw@weilnetz.de>
2012-05-12 14:17:52 +02:00
Blue Swirl 61d25e1548 Merge branch 'qom-cpu-rest.v1' of git://github.com/afaerber/qemu-cpu
* 'qom-cpu-rest.v1' of git://github.com/afaerber/qemu-cpu:
  Makefile: Simplify compilation of target-*/cpu.c
  target-mips: Start QOM'ifying CPU init
  target-mips: QOM'ify CPU
  target-m68k: Add QOM CPU subclasses
  target-m68k: Start QOM'ifying CPU init
  target-m68k: QOM'ify CPU reset
  target-m68k: QOM'ify CPU
  target-sh4: Start QOM'ifying CPU init
  target-sh4: QOM'ify CPU reset
  target-sh4: QOM'ify CPU
  MAINTAINERS: Downgrade target-mips and target-sh4 to Odd Fixes
  MAINTAINERS: Downgrade target-m68k to Odd Fixes
2012-05-01 09:27:53 +00:00
Andreas Färber 0f71a7095d target-mips: QOM'ify CPU
Embed CPUMIPSState as first member of QOM MIPSCPU.

Let CPUClass::reset() call cpu_state_reset() for now.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
2012-04-30 11:32:13 +02:00
Andreas Färber dda3c2ee33 target-mips: Move definition of uint_fast{8, 16}_t to osdep.h
osdep.h is included via qemu-common.h.

Prepares for use of [u]int_fast*_t types in softfloat code.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Cc: Ben Taylor <bentaylor.solx86@gmail.com>
Cc: Aurélien Jarno <aurelien@aurel32.net>
Cc: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Bernhard Walle <bernhard@bwalle.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-04-28 09:12:38 +00:00
Stefan Weil 5cbdb3a34b Replace Qemu by QEMU in comments
The official spelling is QEMU.

Signed-off-by: Stefan Weil <sw@weilnetz.de>
Reviewed-by: Andreas Färber <afaerber@suse.de>
[blauwirbel@gmail.com: fixed comment style in hw/sun4m.c]
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-04-07 14:00:45 +00:00
Andreas Färber 9349b4f9fd Rename CPUState -> CPUArchState
Scripted conversion:
  for file in *.[hc] hw/*.[hc] hw/kvm/*.[hc] linux-user/*.[hc] linux-user/m68k/*.[hc] bsd-user/*.[hc] darwin-user/*.[hc] tcg/*/*.[hc] target-*/cpu.h; do
    sed -i "s/CPUState/CPUArchState/g" $file
  done

All occurrences of CPUArchState are expected to be replaced by QOM CPUState,
once all targets are QOM'ified and common fields have been extracted.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
2012-03-14 22:20:27 +01:00
Andreas Färber 7db13fae2c target-mips: Don't overuse CPUState
Scripted conversion:
  sed -i "s/CPUState/CPUMIPSState/g" target-mips/*.[hc]
  sed -i "s/#define CPUMIPSState/#define CPUState/" target-mips/cpu.h

Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Anthony Liguori <aliguori@us.ibm.com>
2012-03-14 22:20:25 +01:00
Dong Xu Wang 4abf79a428 fix spelling in target sub directory
Cc: Richard Henderson <rth@twiddle.net>
Cc: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Alexander Graf <agraf@suse.de>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Dong Xu Wang <wdongxu@linux.vnet.ibm.com>
Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
2011-12-02 10:50:57 +00:00
Edgar E. Iglesias 344eecf699 mips: Support the MT TCStatus IXMT irq disable flag
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-09-06 11:09:39 +02:00
Edgar E. Iglesias f249412c74 mips: Add MT halting and waking of VPEs
+ some partial support for TC's.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2011-09-06 11:09:39 +02:00
Blue Swirl 97b348e7d2 Remove unused is_softmmu parameter from cpu_handle_mmu_fault
Parameter is_softmmu (and its evil mutant twin brother is_softmuu)
is not used in cpu_*_handle_mmu_fault() functions, remove them
and adjust callers.

Acked-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-08-07 09:32:01 +00:00
Blue Swirl 3e4571724f exec.h cleanup
Move softmmu_exec.h include directives from target-*/exec.h to
target-*/op_helper.c. Move also various other stuff only used in
op_helper.c there.

Define global env in dyngen-exec.h.

For i386, move wrappers for segment and FPU helpers from user-exec.c
to op_helper.c. Implement raise_exception_err_env() to handle dynamic
CPUState. Move the function declarations to cpu.h since they can be
used outside of op_helper.c context.

LM32, s390x, UniCore32: remove unused cpu_halted(), regs_to_env() and
env_to_regs().

ARM: make raise_exception() static.

Convert
#include "exec.h"
to
#include "cpu.h"
#include "dyngen-exec.h"
and remove now unused target-*/exec.h.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-30 09:41:14 +00:00
Blue Swirl b14ef7c9ab Fix unassigned memory access handling
cea5f9a28f exposed bugs in unassigned memory
access handling. Fix them by always passing CPUState to the handlers.

Reported-by: Hervé Poussineau <hpoussin@reactos.org>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-20 21:28:08 +00:00
Blue Swirl f081c76ccf Move cpu_has_work and cpu_pc_from_tb to cpu.h
Move functions cpu_has_work() and cpu_pc_from_tb() from exec.h to cpu.h. This is
needed by later patches.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26 18:25:31 +00:00
Stefan Weil 4ff9786c67 Fix trivial "endianness bugs"
Replace endianess -> endianness.

Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-04-03 21:42:57 +02:00
Aurelien Jarno 4cdc1cd137 target-mips: fix host CPU consumption when guest is idle
When the CPU is in wait state, do not wake-up if an interrupt can't be
taken. This avoid host CPU running at 100% if a device (e.g. timer) has
an interrupt line left enabled.

Also factorize code to check if interrupts are enabled in
cpu_mips_hw_interrupts_pending().

Based on a patch from Edgar E. Iglesias <edgar.iglesias@gmail.com>

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
2010-12-27 00:58:06 +01:00
Stefan Weil 9a78eead0c target-xxx: Use fprintf_function (format checking)
fprintf_function uses format checking with GCC_FMT_ATTR.

Format errors were fixed in
* target-i386/helper.c
* target-mips/translate.c
* target-ppc/translate.c

Cc: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-10-30 08:01:59 +00:00
Edgar E. Iglesias 138afb024b mips: Add support for VInt and VEIC irq modes
Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
2010-08-06 12:21:16 +02:00
Aurelien Jarno 5dc5d9f055 mips: more fixes to the MIPS interrupt glue logic
Commit 36388314fe moved most of the
interrupt logic to cpu-exec.c. Remove the remaining useless code
and fix software interrupts.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Acked-by: Edgar E. Iglesias <edgar@axis.com>
Tested-by: Edgar E. Iglesias <edgar@axis.com>
2010-07-25 16:54:02 +02:00
Edgar E. Iglesias 36388314fe mips: Correct MIPS interrupt glue logic for icount
When hw interrupt pending bits in CP0_Cause are set, the CPU should
see the hw interrupt line as active. The CPU may or may not take the
interrupt based on internal state (global irq mask etc) but the glue
logic shouldn't care.

This fixes MIPS external hw interrupts in combination with -icount.

Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
2010-07-24 13:40:05 +02:00
Paolo Bonzini a88790a14f remove exec-all.h inclusion from cpu.h
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-07-03 09:48:24 +03:00
Paolo Bonzini 10eb0cc03c move cpu_pc_from_tb to target-*/exec.h
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-07-03 09:48:12 +03:00
Nathan Froyd bbfa8f72e9 target-mips: add microMIPS exception handler support
Unlike MIPS16, microMIPS lets you choose the ISA mode for your exception
handlers.  The ISA mode is selectable via a user-writable CP0.Config3
flag.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-06-09 16:10:51 +02:00
Paul Brook 3c7b48b74c Target specific usermode cleanup
Disable various target specific code that is only relevant to system emulation.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-03-12 18:44:24 +00:00
Aurelien Jarno c36bbb28ad target-mips: don't call cpu_loop_exit() from helper.c
In helper.c AREG0 may not correspond do env, so it's not possible to
call cpu_loop_exit() here. Call it from op_helper.c instead.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-02-06 17:23:33 +01:00
Nathan Froyd 79ef2c4cdb target-mips: add new HFLAGs for JALX and 16/32-bit delay slots
We create separate masks for the "basic" branch hflags and the
"extended" branch hflags and define MIPS_HFLAG_BMASK as the logical or
of those two.  This is done to avoid churning the codebase in lots of
different places.

We also make the execution mode an hflag under MIPS_HFLAG_TMASK

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-13 20:20:19 +01:00
Aurelien Jarno 25b91e32e0 target-mips: add a function to do virtual -> physical translations
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-11-30 16:10:04 +01:00
Aurelien Jarno 60c9af07aa target-mips: fix physical address type in MMU functions
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-11-22 14:37:04 +01:00
Aurelien Jarno 2a6e32dd46 target-mips: make CP0_LLAddr register CPU dependent
Depending on the CPU, CP0_LLAddr is either read-only or read-write,
and the returned value can be shifted by a variable amount of bits.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
2009-11-22 14:12:19 +01:00
Aurelien Jarno 5499b6ffac target-mips: rename CP0_LLAddr into lladdr
The variable CP0_LLAddr represent the full lladdr, not the actual
register value, which is only part of this value and depends on the
CPU.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-11-22 14:12:13 +01:00
Blue Swirl 51cc2e783a mips: fix cpu_reset memory leak
Remove cpu_mips_register()
- move mmu_init(), fpu_init() and mvp_init() into cpu_mips_init()
- move the other parts in cpu_mips_init()

Reported-by: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-11-14 02:25:52 +01:00
Anthony Liguori c227f0995e Revert "Get rid of _t suffix"
In the very least, a change like this requires discussion on the list.

The naming convention is goofy and it causes a massive merge problem.  Something
like this _must_ be presented on the list first so people can provide input
and cope with it.

This reverts commit 99a0949b72.

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-01 16:12:16 -05:00
malc 99a0949b72 Get rid of _t suffix
Some not so obvious bits, slirp and Xen were left alone for the time
being.

Signed-off-by: malc <av1474@comtv.ru>
2009-10-01 22:45:02 +04:00
Nathan Froyd 0b5c1ce846 cleanup cpu-exec.c, part 0/N: consolidate handle_cpu_signal
handle_cpu_signal is very nearly copy-paste code for each target, with a
few minor variations.  This patch sets up appropriate defaults for a
generic handle_cpu_signal and provides overrides for particular targets
that did things differently.  Fixing things like the persistent (XXX:
use sigsetjmp) should now become somewhat easier.

Previous comments on this patch suggest that the "activate soft MMU for
this block" comments refer to defunct functionality.  I have removed
such blocks for the appropriate targets in this patch.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-08-24 08:21:42 -05:00
Juan Quintela e2542fe2bc rename WORDS_BIGENDIAN to HOST_WORDS_BIGENDIAN
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-07-27 14:09:21 -05:00
Juan Quintela dfe5fff3ea change HOST_SOLARIS to CONFIG_SOLARIS{_VERSION}
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-07-27 14:09:16 -05:00
Paul Brook 590bc601d8 MIPS atomic instructions
Implement MIPS ll/sc instructions using atomic compare+exchange.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-07-09 17:45:17 +01:00
Paul Brook ff867ddcbd MIPS usermode TLS register
Implement cpu_set_tls for MIPS.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-07-09 15:07:57 +01:00
aurel32 1ba74fb8f1 target-mips: optimize gen_compute_branch()
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6936 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-29 01:18:52 +00:00
aurel32 c01fccd2de target-mips: rename helpers from do_ to helper_
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6773 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-08 00:06:01 +00:00
pbrook c276471991 The _exit syscall is used for both thread termination in NPTL applications,
and process termination in legacy applications.  Try to guess which we want
based on the presence of multiple threads.

Also implement locking when modifying the CPU list.


Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6735 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07 15:24:59 +00:00
ths f9480ffc14 Fix remaining compiler warnings for mips targets.
Signed-off-by: Stefan Weil <weil@mail.berlios.de>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6111 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-20 19:42:14 +00:00