5b50e790f9
cpu: Introduce CPUClass::gdb_{read,write}_register()
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Completes migration of target-specific code to new target-*/gdbstub.c.
Acked-by: Michael Walle <michael@walle.cc> (for lm32)
Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa)
Signed-off-by: Andreas Färber <afaerber@suse.de>
2013-07-27 00:04:17 +02:00
4dd044c6ba
target-or32: Add system instructions
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Add OpenRISC system instructions.
Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-07-27 21:13:03 +00:00
5b5695073b
target-or32: Add float instruction helpers
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Add OpenRISC float instruction helpers.
Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-07-27 21:13:00 +00:00
e54a5aff13
target-or32: Add int instruction helpers
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Add OpenRISC int instruction helpers.
Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-07-27 21:12:59 +00:00
1d7d403469
target-or32: Add exception support
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Add OpenRISC exception support.
Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-07-27 21:12:58 +00:00
b6a71ef7e0
target-or32: Add interrupt support
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Add OpenRISC interrupt support.
Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-07-27 21:12:57 +00:00
e67db06e9f
target-or32: Add target stubs and QOM cpu
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Add OpenRISC target stubs, QOM cpu and basic machine.
Signed-off-by: Jia Liu <proljc@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-07-27 21:12:55 +00:00
Andreas Färber
Jia Liu