Commit Graph

15 Commits

Author SHA1 Message Date
Ankit Kumar 5c69452c14 target-ppc: add vprtyb[w/d/q] instructions
Add following POWER ISA 3.0 instructions.
vprtybw: Vector Parity Byte Word
vprtybd: Vector Parity Byte Double Word
vprtybq: Vector Parity Byte Quad Word

Signed-off-by: Ankit Kumar <ankit@linux.vnet.ibm.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-11-15 10:05:50 +11:00
Bharata B Rao 09a245e187 target-ppc: add vrldnm and vrlwnm instructions
vrldnm: Vector Rotate Left Doubleword then AND with Mask
vrlwnm: Vector Rotate Left Word then AND with Mask

Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-11-15 10:05:50 +11:00
Gautham R. Shenoy 3e00884f4e target-ppc: add vrldnmi and vrlwmi instructions
vrldmi: Vector Rotate Left Dword then Mask Insert
vrlwmi: Vector Rotate Left Word then Mask Insert

Signed-off-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>
Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
( use extract[32,64] and rol[32,64], introduce mask helpers in
  internal.h )
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-11-15 10:05:50 +11:00
Vasant Hegde 37ad52ba7a target-ppc: add vmul10[u,eu,cu,ecu]q instructions
vmul10uq  : Vector Multiply-by-10 Unsigned Quadword VX-form
vmul10euq : Vector Multiply-by-10 Extended Unsigned Quadword VX-form
vmul10cuq : Vector Multiply-by-10 & write Carry Unsigned Quadword VX-form
vmul10ecuq: Vector Multiply-by-10 Extended & write Carry Unsigned Quadword VX-form

Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
[ Add GEN_VXFORM_DUAL_EXT with invalid bit mask ]
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-10-28 09:38:25 +11:00
Nikunj A Dadhania cc8b6e76e3 target-ppc: implement vnegw/d instructions
Vector Integer Negate Instructions:

vnegw: Vector Negate Word
vnegd: Vector Negate Doubleword

Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-10-28 09:36:58 +11:00
Nikunj A Dadhania 125a9b2327 target-ppc: implement vexts[bh]2w and vexts[bhw]2d
Vector Extend Sign Instructions:

vextsb2w: Vector Extend Sign Byte To Word
vextsh2w: Vector Extend Sign Halfword To Word
vextsb2d: Vector Extend Sign Byte To Doubleword
vextsh2d: Vector Extend Sign Halfword To Doubleword
vextsw2d: Vector Extend Sign Word To Doubleword

Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-10-14 10:06:47 +11:00
Nikunj A Dadhania 2020b67d85 target-ppc: fix vmx instruction type/type2
A few of the new instructions added inadvertently changed the type of
old instruction(PPC_ALTIVEC) to PPC2_ALTIVEC_207 in the dual form
declaration.

commit: b5d569a1 (target-ppc: add vector extract instructions)
commit: e7b1e06f (target-ppc: add vector insert instructions)
commit: 3aa56a19 (target-ppc: add vector compare not equal instructions)

New ISA 3.0 instructions added:
    vextractub     PPC_NONE     PPC2_ISA300
    vextractuh     PPC_NONE     PPC2_ISA300
    vextractuw     PPC_NONE     PPC2_ISA300
    vinsertb       PPC_NONE     PPC2_ISA300
    vinserth       PPC_NONE     PPC2_ISA300
    vinsertw       PPC_NONE     PPC2_ISA300
    vcmpneb        PPC_NONE     PPC2_ISA300
    vcmpneh        PPC_NONE     PPC2_ISA300
    vcmpnew        PPC_NONE     PPC2_ISA300

Affected older instructions:
    vspltb         PPC_ALTIVEC  PPC_NONE
    vsplth         PPC_ALTIVEC  PPC_NONE
    vspltw         PPC_ALTIVEC  PPC_NONE
    vspltisb       PPC_ALTIVEC  PPC_NONE
    vspltish       PPC_ALTIVEC  PPC_NONE
    vspltisw       PPC_ALTIVEC  PPC_NONE
    vcmpequb       PPC_ALTIVEC  PPC_NONE
    vcmpequh       PPC_ALTIVEC  PPC_NONE
    vcmpequw       PPC_ALTIVEC  PPC_NONE

Change the instruction type/type2 for the older instructions back to
what it was(PPC_ALTIVEC).

CC: Rajalakshmi Srinivasaraghavan <raji@linux.vnet.ibm.com>
Reported-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-10-05 11:05:28 +11:00
Rajalakshmi Srinivasaraghavan 4879538c99 target-ppc: add vclzlsbb/vctzlsbb instructions
The following vector instructions are added from ISA 3.0.

vclzlsbb - Vector Count Leading Zero Least-Significant Bits Byte
vctzlsbb - Vector Count Trailing Zero Least-Significant Bits Byte

Signed-off-by: Rajalakshmi Srinivasaraghavan <raji@linux.vnet.ibm.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-10-05 11:05:28 +11:00
Rajalakshmi Srinivasaraghavan 0fa5936434 target-ppc: add vector compare not equal instructions
The following vector compare not equal instructions are added from ISA 3.0.

vcmpneb - Vector Compare Not Equal Byte
vcmpneh - Vector Compare Not Equal Halfword
vcmpnew - Vector Compare Not Equal Word

Signed-off-by: Rajalakshmi Srinivasaraghavan <raji@linux.vnet.ibm.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-10-05 11:05:28 +11:00
Rajalakshmi Srinivasaraghavan ab04543602 target-ppc: add vector permute right indexed instruction
Add vpermr instruction from ISA 3.0.

Signed-off-by: Rajalakshmi Srinivasaraghavan <raji@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-23 10:29:40 +10:00
Rajalakshmi Srinivasaraghavan 01fe9a470c target-ppc: add vector bit permute doubleword instruction
Add vbpermd instruction from ISA 3.0.

Signed-off-by: Rajalakshmi Srinivasaraghavan <raji@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-23 10:29:40 +10:00
Rajalakshmi Srinivasaraghavan a5ad8fbf9d target-ppc: add vector count trailing zeros instructions
The following vector count trailing zeros instructions are
added from ISA 3.0.

vctzb - Vector Count Trailing Zeros Byte
vctzh - Vector Count Trailing Zeros Halfword
vctzw - Vector Count Trailing Zeros Word
vctzd - Vector Count Trailing Zeros Doubleword

Signed-off-by: Rajalakshmi Srinivasaraghavan <raji@linux.vnet.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-23 10:29:40 +10:00
Rajalakshmi Srinivasaraghavan b5d569a1bb target-ppc: add vector extract instructions
The following vector extract instructions are added from ISA 3.0.

vextractub - Vector Extract Unsigned Byte
vextractuh - Vector Extract Unsigned Halfword
vextractuw - Vector Extract Unsigned Word
vextractd - Vector Extract Unsigned Doubleword

Signed-off-by: Rajalakshmi Srinivasaraghavan <raji@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-23 10:29:40 +10:00
Rajalakshmi Srinivasaraghavan e7b1e06fbc target-ppc: add vector insert instructions
The following vector insert instructions are added from ISA 3.0.

vinsertb - Vector Insert Byte
vinserth - Vector Insert Halfword
vinsertw - Vector Insert Word
vinsertd - Vector Insert Doubleword

Signed-off-by: Rajalakshmi Srinivasaraghavan <raji@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-23 10:29:40 +10:00
Benjamin Herrenschmidt 15848410af ppc: Rename #include'd .c files to .inc.c
Also while at it, group the #include statements in translate.c

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07 12:40:12 +10:00