Commit Graph

288 Commits

Author SHA1 Message Date
Richard Henderson 09aac1266e tcg/x86_64: Avoid unnecessary REX.B prefixes.
The existing P_REXB internal opcode flag unconditionally emits
the REX prefix.  Technically it's not needed if the register in
question is %al, %bl, %cl, %dl.

Eliding the prefix requires splitting the P_REXB flag into two,
in order to indicate whether the byte register in question is
in the REG or the R/M field.  Within TCG, the byte register is
in the REG field only for stores.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-01-15 07:32:56 +01:00
Richard Henderson 5716990376 tcg/x86_64: Special-case all 32-bit AND operands.
This avoids an unnecessary REX.W prefix when dealing with AND
operands that fit into a 32-bit quantity.  The most common change
actually seen is movz[wb]q -> movz[wb]l.

Similarly, avoid REXW in ext{8,16}u_i64 tcg opcodes.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-01-14 18:16:40 +01:00
Richard Henderson cc6dfecf02 tcg-sparc: Implement ext32[su]_i64
The 32-bit right-shift instructions is defined to extend the shifted
output to 64-bits.  A shift count of zero therefore is a simple
extension without actually shifting.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-01-12 19:59:34 +00:00
Richard Henderson 583d121520 tcg-sparc: Implement division properly.
The {div,divu}2 opcodes are intended for systems for which the
division instruction produces both quotient and remainder.  Sparc
is not such a system.  Indeed, the remainder must be computed as

  quot = a / b
  rem = a - (quot * b)

Split out a tcg_out_div32 function that properly initializes Y
with the extension of the input to 64-bits.  Discard the code
that used the 64-bit DIVX on sparc9/sparcv8plus without extending
the inputs to 64-bits.  Implement remainders in terms of division
followed by multiplication.

Signed-off-by: Richard Henderson <rth@twiddle.net>
[blauwirbel@gmail.com: applied rth's typo fix in tcg_out_div32]
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-01-12 19:59:33 +00:00
Richard Henderson 5e143c43a6 tcg-sparc: Do not remove %o[012] from 'r' constraint.
Only 'L' constraint needs that.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-01-12 19:59:32 +00:00
Richard Henderson 7a3766f390 tcg-sparc: Implement add2, sub2, mulu2.
Add missing 32-bit double-word support opcodes.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-01-12 19:59:31 +00:00
Richard Henderson ba225198d0 tcg-sparc: Add tcg_out_arithc.
Add a function to handle the register-vs-immediate test for arithmetic.

Also, adjust the OP_32_64 macro so that it auto-indents properly.
Rename the gen_arith32 label to gen_arith, since it handles 64-bit
arithmetic as well.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-01-12 19:59:29 +00:00
Richard Henderson ff44c2f3c8 tcg: Add tcg_unsigned_cond.
Returns an unsigned version of a signed condition;
returns the original condition otherwise.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-12-27 09:09:41 +00:00
Richard Henderson 56f4927e34 tcg-sparc: Implement brcond2.
Split out tcg_out_cmp and properly handle immediate arguments.
Fix constraints on brcond to match what SUBCC accepts.
Add tcg_out_brcond2_i32 for 32-bit host.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-12-21 20:52:36 +00:00
Richard Henderson a212ea7553 tcg-sparc: Use TCG_TARGET_REG_BITS in conditional compilation.
The test TCG_TARGET_REG_BITS==64 is exactly the feature that we
are checking for, whereas something involving __sparc_v9__ or
__sparc_v8plus__ should be reserved for something ISA related,
as with SMULX.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-12-21 20:52:34 +00:00
Richard Henderson 431722077a tcg-sparc: Improve tcg_out_movi for sparc64.
Generate sign-extended 32-bit constants with SETHI+XOR.
Otherwise tidy the routine to avoid the need for
conditional compilation and code duplication with movi_imm32.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-12-21 20:52:06 +00:00
Richard Henderson 4a09aa895e tcg-sparc: Fix imm13 check in movi.
We were unnecessarily restricting imm13 constants to 12 bits.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-12-21 20:49:34 +00:00
malc 591d6f1dfd tcg/ppc64: Fix loading of 32bit constants
Signed-off-by: malc <av1474@comtv.ru>
2009-12-15 19:45:28 +03:00
Andreas Faerber 5d7ff5bbde TCG: Mac OS X support for ppc64 target
Darwin/ppc64 does not use function descriptors,
adapt prologue and tcg_out_call accordingly.
GPR2 is available for general use, so let's use it.

http://developer.apple.com/mac/library/documentation/DeveloperTools/Conceptual/LowLevelABI/110-64-bit_PowerPC_Function_Calling_Conventions/64bitPowerPC.html

v2:
- Don't mark reserved GPR13 as callee-save.
- Move tcg_out_b up.
- Fix unused variable warning in prologue.

Signed-off-by: Andreas Faerber <andreas.faerber@web.de>
Cc: malc <av1474@comtv.ru>
Signed-off-by: malc <av1474@comtv.ru>
2009-12-06 18:20:26 +03:00
Alexander Graf 2827822ef1 S/390 fake TCG implementation
Qemu won't let us run a KVM target without having host TCG support. Well, for
now we don't have any so let's implement a fake target that only stubs out
everything.

I tried to keep the patch as close to Uli's source as possible, so whenever
he feels like it he can easily diff his version against this one.

Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-05 17:36:00 +01:00
Aurelien Jarno afa05235a5 tcg: initial mips support
Based on a patch from Arnaud Patard (Rtp) <arnaud.patard@rtp-net.org>

A few words about design choices:
* Two registers, at and t0, are reserved for TCG internal use. They are
  useful for bswap and 64-bit ops.
* Most ops supports a constant argument with value 0, which is actually
  mapped to the zero register.
* While the at register is available for constant loading, ops only
  support a limited range of constants. TCG does a better job doing the
  register allocation and constant loading by itself. There are plenty of
  registers available anyway.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-12-01 00:06:15 +00:00
Aurelien Jarno 7d30175271 tcg: fix tcg_regset_{set,reset}_reg with more than 32 registers
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-11-24 19:51:13 +01:00
Aurelien Jarno 016b2b287d tcg/ppc64,x86_64: fix constraints of op_qemu_st64
This op only takes two arguments, not two.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-11-24 19:51:12 +01:00
Magnus Damm b785e4768b tcg/i386: remove duplicate sar opcode
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-11-14 01:17:47 +01:00
Aurelien Jarno 6a957025eb tcg: improve output log
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-07 07:53:41 +02:00
Aurelien Jarno 94f4af02a1 tcg: allocate s->op_dead_iargs dynamically
Similarly to what is already done in tcg_liveness_analysis() when
USE_LIVENESS_ANALYSIS is not set.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-04 15:30:44 +02:00
Aurelien Jarno 8389c67b82 tcg: remove dead code
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-04 15:16:46 +02:00
Aurelien Jarno 5f0ce17ffc tcg/i386: add support for ext{8,16}u_i32 TCG ops
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-04 13:24:45 +02:00
Aurelien Jarno 6458421802 tcg/x86_64: add support for ext{8,16,32}u_i{32,64} TCG ops
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-04 13:24:45 +02:00
Aurelien Jarno cfc86988a8 tcg: add ext{8,16,32}u_i{32,64} TCG ops
Currently zero extensions ops are implemented by a and op with a
constant. This is then catched in some backend, and replaced by
a zero extension instruction. While this works well on RISC
machines, this adds a useless register move on non-RISC machines.

Example on x86:
  ext16u_i32 r1, r2
is translated into
  mov    %eax,%ebx
  movzwl %bx, %ebx
while the optimized version should be:
  movzwl %ax, %ebx

This patch adds ext{8,16,32}u_i{32,64} TCG ops that can be
implemented in the backends to avoid emitting useless register
moves.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-04 13:24:45 +02:00
Aurelien Jarno d68592022b Revert part of 6692b04319
Committed by accident.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-30 14:16:12 +02:00
Aurelien Jarno 6692b04319 TCG: fix DEF2 macro
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-30 14:10:34 +02:00
Aurelien Jarno 17cf428f2e tcg/i386: generates dec/inc instead of sub/add when possible
We must take care that dec/inc do not compute CF, which is needed by
add2/sub2.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-27 20:00:39 +02:00
Aurelien Jarno b70650cbfe tcg/i386: optimize and $0xff(ff), reg
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-27 20:00:38 +02:00
Aurelien Jarno a4b18c6ddb tcg/x86_64: generated dec/inc instead of sub/add when possible
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-27 18:08:16 +02:00
malc d937032764 tcg/ppc: always use tcg_out_call
Signed-off-by: malc <av1474@comtv.ru>
2009-09-27 14:41:14 +04:00
Laurent Desnogues 7990496dcb ARM back-end: Use sxt[bh] instructions for ext{8, 6}s
This patch uses sxtb for ext8s_i32 and sxth for ext16s_i32 in ARM back-end.

Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-26 21:29:59 +02:00
Stefan Weil d89c682f20 Suppress some variants of English in comments
Replace surpress, supress by suppress.

Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-25 16:31:35 +02:00
Blue Swirl 96e132e24e Compile TCG runtime library only once
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-09-20 19:06:34 +00:00
Stefan Weil b348113d21 tcg: fix size of local variables in tcg_gen_bswap64_i64
t0, t1 must be 64 bit values, not 32 bit.

Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-09-16 21:26:47 +02:00
malc abb6ae2c00 X86_64: Use proper jumps/calls when displacement exceeds +-2G
Signed-off-by: malc <av1474@comtv.ru>
2009-09-11 01:38:52 +04:00
malc c45851c44a When targeting PPU use rlwinm instead of andi. if possible
andi. is microcoded and slow there.

Signed-off-by: malc <av1474@comtv.ru>
2009-09-06 07:24:37 +04:00
Laurent Desnogues 4e6f6d4c20 ARM back-end: Fix encode_imm
the encode_imm function in tcg/arm/tcg-target.c lacks shift declaration.

Laurent

Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2009-08-25 01:14:14 +02:00
Laurent Desnogues 94953e6d74 ARM back-end: Handle all possible immediates for ALU ops
this patch handles all possible constants for immediate operand of ALU ops.
I'm not very satisfied by the implementation.

Laurent

Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2009-08-22 14:29:09 +02:00
Laurent Desnogues f878d2d235 ARM back-end: Add TCG not
this patch:

 - implements TCG not.

Laurent

Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2009-08-22 13:55:06 +02:00
Juan Quintela e2542fe2bc rename WORDS_BIGENDIAN to HOST_WORDS_BIGENDIAN
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-07-27 14:09:21 -05:00
Juan Quintela 092c73eeff rename DEBUG_TCG to CONFIG_DEBUG_TCG
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-07-27 14:09:21 -05:00
Juan Quintela dfe5fff3ea change HOST_SOLARIS to CONFIG_SOLARIS{_VERSION}
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-07-27 14:09:16 -05:00
Blue Swirl 871e6c3507 Fix CONFIG_PROFILER
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-07-21 12:18:03 +00:00
malc a71836de38 Fix rbase initialization
Signed-off-by: malc <av1474@comtv.ru>
2009-07-20 01:15:23 +04:00
Laurent Desnogues cb4e581fae this patch improves the ARM back-end in the following way:
- use movw/movt to load immediate values for ARMv7-A
- implement add/sub/and/or/xor with immediate (only 8-bit)

Laurent

Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
2009-07-18 14:20:30 +02:00
Aurelien Jarno d9885a0b9e tcg: Fix tcg_gen_rotr_i64
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-07-18 11:32:56 +02:00
malc f6548c0a4b PPC 32/64 GUEST_BASE support
Signed-off-by: malc <av1474@comtv.ru>
2009-07-18 13:16:36 +04:00
malc 4f4a67ae78 Fix LHZX opcode value
Signed-off-by: malc <av1474@comtv.ru>
2009-07-18 13:16:13 +04:00
Juan Quintela adea8197b4 Userspace guest address offsetting
Fix type in i386 tcg.

Signed-off-by: Juan Quintela <quintela@redhat.com>
2009-07-17 19:50:18 +01:00