Commit Graph

3 Commits

Author SHA1 Message Date
Max Filippov 906da88291 tests/tcg/xtensa: support configurations w/o vecbase
Configurations w/o vecbase may have vectors not grouped together and not
in fixed order. They may not always be grouped into single output
sections by assigning next offset to dot, as it may sometimes move dot
backwards and sometimes they may even belong to different memory region.
Don't group vectors into single output section. Instead put each vector
into its own section ant put it at its default virtual address.
Reserve 4KBytes from the default vectors base and put rest of the code
and data starting from there. Mark vectors sections as executable,
otherwise their contents is discarded. There may be as little as 16
bytes reserved for some vectors, load handler address into a0 and use
ret.n to jump there to make vector code fit into this 16 byte space.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-02-28 04:43:22 -08:00
Max Filippov f68774ccd8 tests/tcg/xtensa: only generate defined exception handlers
Don't generate handlers for IRQ levels that are not defined for the CPU
or for window overflow/underflow exceptions for configs w/o windowed
registers.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2018-09-17 11:09:04 -07:00
Anthony Liguori c09015dd04 tests: mv tests/* -> tests/tcg
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-01-12 10:03:28 -06:00