/* * OpenRISC cpu parameters for qemu. * * Copyright (c) 2011-2012 Jia Liu * SPDX-License-Identifier: LGPL-2.0+ */ #ifndef OPENRISC_CPU_PARAM_H #define OPENRISC_CPU_PARAM_H #define TARGET_LONG_BITS 32 #define TARGET_PAGE_BITS 13 #define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 #define NB_MMU_MODES 3 #endif