/* * Generic vector operation descriptor * * Copyright (c) 2018 Linaro * * This library is free software; you can redistribute it and/or * modify it under the terms of the GNU Lesser General Public * License as published by the Free Software Foundation; either * version 2.1 of the License, or (at your option) any later version. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * Lesser General Public License for more details. * * You should have received a copy of the GNU Lesser General Public * License along with this library; if not, see <http://www.gnu.org/licenses/>. */ #ifndef TCG_TCG_GVEC_DESC_H #define TCG_TCG_GVEC_DESC_H /* * This configuration allows MAXSZ to represent 2048 bytes, and * OPRSZ to match MAXSZ, or represent the smaller values 8, 16, or 32. * * Encode this with: * 0, 1, 3 -> 8, 16, 32 * 2 -> maxsz * * This steals the input that would otherwise map to 24 to match maxsz. */ #define SIMD_MAXSZ_SHIFT 0 #define SIMD_MAXSZ_BITS 8 #define SIMD_OPRSZ_SHIFT (SIMD_MAXSZ_SHIFT + SIMD_MAXSZ_BITS) #define SIMD_OPRSZ_BITS 2 #define SIMD_DATA_SHIFT (SIMD_OPRSZ_SHIFT + SIMD_OPRSZ_BITS) #define SIMD_DATA_BITS (32 - SIMD_DATA_SHIFT) /* Create a descriptor from components. */ uint32_t simd_desc(uint32_t oprsz, uint32_t maxsz, int32_t data); /* Extract the max vector size from a descriptor. */ static inline intptr_t simd_maxsz(uint32_t desc) { return extract32(desc, SIMD_MAXSZ_SHIFT, SIMD_MAXSZ_BITS) * 8 + 8; } /* Extract the operation size from a descriptor. */ static inline intptr_t simd_oprsz(uint32_t desc) { uint32_t f = extract32(desc, SIMD_OPRSZ_SHIFT, SIMD_OPRSZ_BITS); intptr_t o = f * 8 + 8; intptr_t m = simd_maxsz(desc); return f == 2 ? m : o; } /* Extract the operation-specific data from a descriptor. */ static inline int32_t simd_data(uint32_t desc) { return sextract32(desc, SIMD_DATA_SHIFT, SIMD_DATA_BITS); } #endif