166 lines
6.5 KiB
C
166 lines
6.5 KiB
C
/* Support for generating ACPI tables and passing them to Guests
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*
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* Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
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* Copyright (C) 2006 Fabrice Bellard
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* Copyright (C) 2013 Red Hat Inc
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*
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* Author: Michael S. Tsirkin <mst@redhat.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "exec/memory.h"
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#include "hw/acpi/acpi.h"
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#include "hw/acpi/aml-build.h"
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#include "hw/acpi/utils.h"
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#include "hw/i386/pc.h"
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#include "target/i386/cpu.h"
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#include "acpi-build.h"
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#include "acpi-common.h"
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void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid,
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const CPUArchIdList *apic_ids, GArray *entry,
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bool force_enabled)
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{
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uint32_t apic_id = apic_ids->cpus[uid].arch_id;
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/* Flags – Local APIC Flags */
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uint32_t flags = apic_ids->cpus[uid].cpu != NULL || force_enabled ?
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1 /* Enabled */ : 0;
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/* ACPI spec says that LAPIC entry for non present
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* CPU may be omitted from MADT or it must be marked
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* as disabled. However omitting non present CPU from
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* MADT breaks hotplug on linux. So possible CPUs
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* should be put in MADT but kept disabled.
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*/
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if (apic_id < 255) {
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/* Rev 1.0b, Table 5-13 Processor Local APIC Structure */
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build_append_int_noprefix(entry, 0, 1); /* Type */
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build_append_int_noprefix(entry, 8, 1); /* Length */
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build_append_int_noprefix(entry, uid, 1); /* ACPI Processor ID */
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build_append_int_noprefix(entry, apic_id, 1); /* APIC ID */
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build_append_int_noprefix(entry, flags, 4); /* Flags */
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} else {
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/* Rev 4.0, 5.2.12.12 Processor Local x2APIC Structure */
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build_append_int_noprefix(entry, 9, 1); /* Type */
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build_append_int_noprefix(entry, 16, 1); /* Length */
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build_append_int_noprefix(entry, 0, 2); /* Reserved */
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build_append_int_noprefix(entry, apic_id, 4); /* X2APIC ID */
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build_append_int_noprefix(entry, flags, 4); /* Flags */
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build_append_int_noprefix(entry, uid, 4); /* ACPI Processor UID */
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}
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}
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static void build_ioapic(GArray *entry, uint8_t id, uint32_t addr, uint32_t irq)
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{
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/* Rev 1.0b, 5.2.8.2 IO APIC */
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build_append_int_noprefix(entry, 1, 1); /* Type */
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build_append_int_noprefix(entry, 12, 1); /* Length */
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build_append_int_noprefix(entry, id, 1); /* IO APIC ID */
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build_append_int_noprefix(entry, 0, 1); /* Reserved */
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build_append_int_noprefix(entry, addr, 4); /* IO APIC Address */
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build_append_int_noprefix(entry, irq, 4); /* System Vector Base */
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}
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static void
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build_xrupt_override(GArray *entry, uint8_t src, uint32_t gsi, uint16_t flags)
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{
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/* Rev 1.0b, 5.2.8.3.1 Interrupt Source Overrides */
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build_append_int_noprefix(entry, 2, 1); /* Type */
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build_append_int_noprefix(entry, 10, 1); /* Length */
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build_append_int_noprefix(entry, 0, 1); /* Bus */
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build_append_int_noprefix(entry, src, 1); /* Source */
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/* Global System Interrupt Vector */
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build_append_int_noprefix(entry, gsi, 4);
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build_append_int_noprefix(entry, flags, 2); /* Flags */
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}
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/*
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* ACPI spec, Revision 1.0b
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* 5.2.8 Multiple APIC Description Table
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*/
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void acpi_build_madt(GArray *table_data, BIOSLinker *linker,
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X86MachineState *x86ms, AcpiDeviceIf *adev,
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const char *oem_id, const char *oem_table_id)
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{
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int i;
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bool x2apic_mode = false;
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MachineClass *mc = MACHINE_GET_CLASS(x86ms);
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const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(MACHINE(x86ms));
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AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_GET_CLASS(adev);
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AcpiTable table = { .sig = "APIC", .rev = 1, .oem_id = oem_id,
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.oem_table_id = oem_table_id };
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acpi_table_begin(&table, table_data);
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/* Local APIC Address */
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build_append_int_noprefix(table_data, APIC_DEFAULT_ADDRESS, 4);
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build_append_int_noprefix(table_data, 1 /* PCAT_COMPAT */, 4); /* Flags */
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for (i = 0; i < apic_ids->len; i++) {
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adevc->madt_cpu(adev, i, apic_ids, table_data, false);
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if (apic_ids->cpus[i].arch_id > 254) {
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x2apic_mode = true;
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}
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}
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build_ioapic(table_data, ACPI_BUILD_IOAPIC_ID, IO_APIC_DEFAULT_ADDRESS, 0);
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if (x86ms->ioapic2) {
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build_ioapic(table_data, ACPI_BUILD_IOAPIC_ID + 1,
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IO_APIC_SECONDARY_ADDRESS, IO_APIC_SECONDARY_IRQBASE);
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}
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if (x86ms->apic_xrupt_override) {
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build_xrupt_override(table_data, 0, 2,
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0 /* Flags: Conforms to the specifications of the bus */);
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}
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for (i = 1; i < 16; i++) {
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if (!(x86ms->pci_irq_mask & (1 << i))) {
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/* No need for a INT source override structure. */
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continue;
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}
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build_xrupt_override(table_data, i, i,
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0xd /* Flags: Active high, Level Triggered */);
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}
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if (x2apic_mode) {
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/* Rev 4.0, 5.2.12.13 Local x2APIC NMI Structure*/
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build_append_int_noprefix(table_data, 0xA, 1); /* Type */
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build_append_int_noprefix(table_data, 12, 1); /* Length */
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build_append_int_noprefix(table_data, 0, 2); /* Flags */
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/* ACPI Processor UID */
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build_append_int_noprefix(table_data, 0xFFFFFFFF /* all processors */,
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4);
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/* Local x2APIC LINT# */
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build_append_int_noprefix(table_data, 1 /* ACPI_LINT1 */, 1);
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build_append_int_noprefix(table_data, 0, 3); /* Reserved */
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} else {
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/* Rev 1.0b, 5.2.8.3.3 Local APIC NMI */
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build_append_int_noprefix(table_data, 4, 1); /* Type */
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build_append_int_noprefix(table_data, 6, 1); /* Length */
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/* ACPI Processor ID */
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build_append_int_noprefix(table_data, 0xFF /* all processors */, 1);
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build_append_int_noprefix(table_data, 0, 2); /* Flags */
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/* Local APIC INTI# */
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build_append_int_noprefix(table_data, 1 /* ACPI_LINT1 */, 1);
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}
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acpi_table_end(linker, &table);
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}
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