3b4fff1bd5
Convert the sparc CPU class to use 3-phase reset, so it doesn't need to use device_class_set_parent_reset() any more. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-id: 20221124115023.2437291-18-peter.maydell@linaro.org
54 lines
1.4 KiB
C
54 lines
1.4 KiB
C
/*
|
|
* QEMU SPARC CPU
|
|
*
|
|
* Copyright (c) 2012 SUSE LINUX Products GmbH
|
|
*
|
|
* This library is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU Lesser General Public
|
|
* License as published by the Free Software Foundation; either
|
|
* version 2.1 of the License, or (at your option) any later version.
|
|
*
|
|
* This library is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
|
* Lesser General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU Lesser General Public
|
|
* License along with this library; if not, see
|
|
* <http://www.gnu.org/licenses/lgpl-2.1.html>
|
|
*/
|
|
#ifndef QEMU_SPARC_CPU_QOM_H
|
|
#define QEMU_SPARC_CPU_QOM_H
|
|
|
|
#include "hw/core/cpu.h"
|
|
#include "qom/object.h"
|
|
|
|
#ifdef TARGET_SPARC64
|
|
#define TYPE_SPARC_CPU "sparc64-cpu"
|
|
#else
|
|
#define TYPE_SPARC_CPU "sparc-cpu"
|
|
#endif
|
|
|
|
OBJECT_DECLARE_CPU_TYPE(SPARCCPU, SPARCCPUClass, SPARC_CPU)
|
|
|
|
typedef struct sparc_def_t sparc_def_t;
|
|
/**
|
|
* SPARCCPUClass:
|
|
* @parent_realize: The parent class' realize handler.
|
|
* @parent_phases: The parent class' reset phase handlers.
|
|
*
|
|
* A SPARC CPU model.
|
|
*/
|
|
struct SPARCCPUClass {
|
|
/*< private >*/
|
|
CPUClass parent_class;
|
|
/*< public >*/
|
|
|
|
DeviceRealize parent_realize;
|
|
ResettablePhases parent_phases;
|
|
sparc_def_t *cpu_def;
|
|
};
|
|
|
|
|
|
#endif
|