b4ecda2dd7
Add a model of the Xilinx ZynqMP APU Control. Reviewed-by: Luc Michel <luc@lmichel.fr> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20220316164645.2303510-6-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
94 lines
2.4 KiB
C
94 lines
2.4 KiB
C
/*
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* QEMU model of ZynqMP APU Control.
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*
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* Copyright (c) 2013-2022 Xilinx Inc
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* SPDX-License-Identifier: GPL-2.0-or-later
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*
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* Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> and
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* Edgar E. Iglesias <edgar.iglesias@xilinx.com>
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*
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*/
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#ifndef HW_MISC_XLNX_ZYNQMP_APU_CTRL_H
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#define HW_MISC_XLNX_ZYNQMP_APU_CTRL_H
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#include "hw/sysbus.h"
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#include "hw/register.h"
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#include "target/arm/cpu.h"
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#define TYPE_XLNX_ZYNQMP_APU_CTRL "xlnx.apu-ctrl"
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OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPAPUCtrl, XLNX_ZYNQMP_APU_CTRL)
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REG32(APU_ERR_CTRL, 0x0)
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FIELD(APU_ERR_CTRL, PSLVERR, 0, 1)
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REG32(ISR, 0x10)
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FIELD(ISR, INV_APB, 0, 1)
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REG32(IMR, 0x14)
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FIELD(IMR, INV_APB, 0, 1)
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REG32(IEN, 0x18)
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FIELD(IEN, INV_APB, 0, 1)
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REG32(IDS, 0x1c)
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FIELD(IDS, INV_APB, 0, 1)
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REG32(CONFIG_0, 0x20)
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FIELD(CONFIG_0, CFGTE, 24, 4)
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FIELD(CONFIG_0, CFGEND, 16, 4)
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FIELD(CONFIG_0, VINITHI, 8, 4)
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FIELD(CONFIG_0, AA64NAA32, 0, 4)
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REG32(CONFIG_1, 0x24)
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FIELD(CONFIG_1, L2RSTDISABLE, 29, 1)
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FIELD(CONFIG_1, L1RSTDISABLE, 28, 1)
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FIELD(CONFIG_1, CP15DISABLE, 0, 4)
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REG32(RVBARADDR0L, 0x40)
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FIELD(RVBARADDR0L, ADDR, 2, 30)
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REG32(RVBARADDR0H, 0x44)
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FIELD(RVBARADDR0H, ADDR, 0, 8)
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REG32(RVBARADDR1L, 0x48)
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FIELD(RVBARADDR1L, ADDR, 2, 30)
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REG32(RVBARADDR1H, 0x4c)
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FIELD(RVBARADDR1H, ADDR, 0, 8)
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REG32(RVBARADDR2L, 0x50)
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FIELD(RVBARADDR2L, ADDR, 2, 30)
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REG32(RVBARADDR2H, 0x54)
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FIELD(RVBARADDR2H, ADDR, 0, 8)
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REG32(RVBARADDR3L, 0x58)
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FIELD(RVBARADDR3L, ADDR, 2, 30)
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REG32(RVBARADDR3H, 0x5c)
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FIELD(RVBARADDR3H, ADDR, 0, 8)
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REG32(ACE_CTRL, 0x60)
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FIELD(ACE_CTRL, AWQOS, 16, 4)
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FIELD(ACE_CTRL, ARQOS, 0, 4)
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REG32(SNOOP_CTRL, 0x80)
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FIELD(SNOOP_CTRL, ACE_INACT, 4, 1)
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FIELD(SNOOP_CTRL, ACP_INACT, 0, 1)
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REG32(PWRCTL, 0x90)
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FIELD(PWRCTL, CLREXMONREQ, 17, 1)
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FIELD(PWRCTL, L2FLUSHREQ, 16, 1)
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FIELD(PWRCTL, CPUPWRDWNREQ, 0, 4)
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REG32(PWRSTAT, 0x94)
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FIELD(PWRSTAT, CLREXMONACK, 17, 1)
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FIELD(PWRSTAT, L2FLUSHDONE, 16, 1)
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FIELD(PWRSTAT, DBGNOPWRDWN, 0, 4)
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#define APU_R_MAX ((R_PWRSTAT) + 1)
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#define APU_MAX_CPU 4
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struct XlnxZynqMPAPUCtrl {
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SysBusDevice busdev;
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ARMCPU *cpus[APU_MAX_CPU];
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/* WFIs towards PMU. */
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qemu_irq wfi_out[4];
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/* CPU Power status towards INTC Redirect. */
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qemu_irq cpu_power_status[4];
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qemu_irq irq_imr;
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uint8_t cpu_pwrdwn_req;
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uint8_t cpu_in_wfi;
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RegisterInfoArray *reg_array;
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uint32_t regs[APU_R_MAX];
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RegisterInfo regs_info[APU_R_MAX];
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};
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#endif
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