Francisco Iglesias 1f1a7b2269 include/hw/pci/pcie_host: Correct PCIE_MMCFG_SIZE_MAX ... According to 7.2.2 in [1] bit 27 is the last bit that can be part of the bus number, this makes the ECAM max size equal to '1 << 28'. This patch restores back this value into the PCIE_MMCFG_SIZE_MAX define (which was changed in commit 58d5b22bbd ("ppc4xx: Add device models found in PPC440 core SoCs")). [1] PCI Express® Base Specification Revision 5.0 Version 1.0 Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com> Message-Id: <20220411221836.17699-3-frasse.iglesias@gmail.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>		2022-05-16 16:15:40 -04:00
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msi.h
msix.h
pci_bridge.h	acpi/cxl: Create the CEDT (9.14.1)	2022-05-13 06:13:36 -04:00
pci_bus.h	hw/pci/cxl: Create a CXL bus type	2022-05-13 06:13:36 -04:00
pci_host.h	hw/pci/pci_host: Allow PCI host to bypass iommu	2021-07-16 11:10:45 -04:00
pci_ids.h	hw/cxl/device: Add a memory device (8.2.8.5)	2022-05-13 06:13:36 -04:00
pci_regs.h	pcie: Add 1.2 version token for the Power Management Capability	2022-03-06 05:08:23 -05:00
pci.h	hw/pxb: Allow creation of a CXL PXB (host bridge)	2022-05-13 06:13:36 -04:00
pcie_aer.h
pcie_host.h	include/hw/pci/pcie_host: Correct PCIE_MMCFG_SIZE_MAX	2022-05-16 16:15:40 -04:00
pcie_port.h	pci/pcie_port: Add pci_find_port_by_pn()	2022-05-13 07:57:26 -04:00
pcie_regs.h
pcie_sriov.h	pcie: Add a helper to the SR/IOV API	2022-03-06 05:08:23 -05:00
pcie.h	acpi: pcihp: pcie: set power on cap on parent slot	2022-03-06 05:08:23 -05:00
shpc.h
slotid_cap.h