115 lines
4.4 KiB
Plaintext
115 lines
4.4 KiB
Plaintext
Generic PCI Express to PCI Bridge
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================================
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Description
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===========
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PCIE-to-PCI bridge is a new method for legacy PCI
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hierarchies creation on Q35 machines.
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Previously Intel DMI-to-PCI bridge was used for this purpose.
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But due to its strict limitations - no support of hot-plug,
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no cross-platform and cross-architecture support - a new generic
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PCIE-to-PCI bridge should now be used for any legacy PCI device usage
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with PCI Express machine.
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This generic PCIE-PCI bridge is a cross-platform device,
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can be hot-plugged into appropriate root port (requires additional actions,
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see 'PCIE-PCI bridge hot-plug' section),
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and supports devices hot-plug into the bridge itself
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(with some limitations, see below).
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Hot-plug of legacy PCI devices into the bridge
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is provided by bridge's built-in Standard hot-plug Controller.
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Though it still has some limitations, see below.
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PCIE-PCI bridge hot-plug
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=======================
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Guest OSes require extra efforts to enable PCIE-PCI bridge hot-plug.
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Motivation - now on init any PCI Express root port which doesn't have
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any device plugged in, has no free buses reserved to provide any of them
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to a hot-plugged devices in future.
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To solve this problem we reserve additional buses on a firmware level.
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Currently only SeaBIOS is supported.
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The way of bus number to reserve delivery is special
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Red Hat vendor-specific PCI capability, added to the root port
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that is planned to have PCIE-PCI bridge hot-plugged in.
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Capability layout (defined in include/hw/pci/pci_bridge.h):
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uint8_t id; Standard PCI capability header field
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uint8_t next; Standard PCI capability header field
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uint8_t len; Standard PCI vendor-specific capability header field
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uint8_t type; Red Hat vendor-specific capability type
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List of currently existing types:
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RESOURCE_RESERVE = 1
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uint32_t bus_res; Minimum number of buses to reserve
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uint64_t io; IO space to reserve
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uint32_t mem Non-prefetchable memory to reserve
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At most one of the following two fields may be set to a value
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different from -1:
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uint32_t mem_pref_32; Prefetchable memory to reserve (32-bit MMIO)
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uint64_t mem_pref_64; Prefetchable memory to reserve (64-bit MMIO)
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If any reservation field is -1 then this kind of reservation is not
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needed and must be ignored by firmware.
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At the moment this capability is used only in QEMU generic PCIe root port
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(-device pcie-root-port). Capability construction function takes all reservation
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fields values from corresponding device properties. By default all of them are
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set to -1 to leave root port's default behavior unchanged.
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Usage
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=====
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A detailed command line would be:
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[qemu-bin + storage options] \
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-m 2G \
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-device pcie-root-port,bus=pcie.0,id=rp1 \
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-device pcie-root-port,bus=pcie.0,id=rp2 \
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-device pcie-root-port,bus=pcie.0,id=rp3,bus-reserve=1 \
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-device pcie-pci-bridge,id=br1,bus=rp1 \
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-device pcie-pci-bridge,id=br2,bus=rp2 \
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-device e1000,bus=br1,addr=8
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Then in monitor it's OK to execute next commands:
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device_add pcie-pci-bridge,id=br3,bus=rp3 \
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device_add e1000,bus=br2,addr=1 \
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device_add e1000,bus=br3,addr=1
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Here you have:
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(1) Cold-plugged:
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- Root ports: 1 QEMU generic root port with the capability mentioned above,
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2 QEMU generic root ports without this capability;
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- 2 PCIE-PCI bridges plugged into 2 different root ports;
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- e1000 plugged into the first bridge.
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(2) Hot-plugged:
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- PCIE-PCI bridge, plugged into QEMU generic root port;
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- 2 e1000 cards, one plugged into the cold-plugged PCIE-PCI bridge,
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another plugged into the hot-plugged bridge.
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Limitations
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===========
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The PCIE-PCI bridge can be hot-plugged only into pcie-root-port that
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has proper 'bus-reserve' property value to provide secondary bus for the
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hot-plugged bridge.
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Windows 7 and older versions don't support hot-plug devices into the PCIE-PCI bridge.
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To enable device hot-plug into the bridge on Linux there're 3 ways:
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1) Build shpchp module with this patch http://www.spinics.net/lists/linux-pci/msg63052.html
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2) Use kernel 4.14+ where the patch mentioned above is already merged.
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3) Set 'msi' property to off - this forces the bridge to use legacy INTx,
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which allows the bridge to notify the OS about hot-plug event without having
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BUSMASTER set.
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Implementation
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==============
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The PCIE-PCI bridge is based on PCI-PCI bridge, but also accumulates PCI Express
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features as a PCI Express device (is_express=1).
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