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qemu-e2k/target/openrisc
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Richard Henderson 01ec3ec930 target/openrisc: Exit the TB after l.mtspr 
A store to SR changes interrupt state, which should return
to the main loop to recognize that state.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
 		2018-07-03 00:05:28 +09:00
..
Makefile.objs target/openrisc: Add print_insn_or1k 2018-07-03 00:05:28 +09:00
cpu.c target/openrisc: Add print_insn_or1k 2018-07-03 00:05:28 +09:00
cpu.h target/openrisc: Add print_insn_or1k 2018-07-03 00:05:28 +09:00
disas.c target/openrisc: Add print_insn_or1k 2018-07-03 00:05:28 +09:00
exception.c Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
exception.h Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
exception_helper.c misc: remove duplicated includes 2017-12-18 17:07:02 +03:00
fpu_helper.c target-openrisc: Write back result before FPE exception 2018-05-14 14:35:02 -07:00
gdbstub.c target/openrisc: implement shadow registers 2017-05-04 09:39:01 +09:00
helper.h target-openrisc: Write back result before FPE exception 2018-05-14 14:35:02 -07:00
insns.decode target/openrisc: Convert dec_float 2018-05-14 14:55:29 -07:00
interrupt.c target/openrisc: Log interrupts 2018-07-03 00:05:28 +09:00
interrupt_helper.c target/openrisc: Use exit_tb instead of CPU_INTERRUPT_EXITTB 2018-07-03 00:05:28 +09:00
machine.c openrisc/cputimer: Perparation for Multicore 2017-10-21 06:35:47 +09:00
mmu.c accel/tcg: add size paremeter in tlb_fill() 2018-01-25 16:02:24 +01:00
mmu_helper.c accel/tcg: add size paremeter in tlb_fill() 2018-01-25 16:02:24 +01:00
sys_helper.c target/openrisc: Fix mtspr shadow gprs 2018-07-02 22:31:59 +09:00
translate.c target/openrisc: Exit the TB after l.mtspr 2018-07-03 00:05:28 +09:00