224 lines
7.2 KiB
C
224 lines
7.2 KiB
C
/*
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* Q35 chipset based pc system emulator
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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* Copyright (c) 2009, 2010
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* Isaku Yamahata <yamahata at valinux co jp>
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* VA Linux Systems Japan K.K.
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* Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
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*
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* This is based on pc.c, but heavily modified.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h"
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#include "arch_init.h"
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#include "smbus.h"
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#include "boards.h"
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#include "mc146818rtc.h"
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#include "xen.h"
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#include "kvm.h"
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#include "kvm/clock.h"
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#include "q35.h"
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#include "exec/address-spaces.h"
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#include "ich9.h"
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#include "hw/ide/pci.h"
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#include "hw/ide/ahci.h"
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#include "hw/usb.h"
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/* ICH9 AHCI has 6 ports */
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#define MAX_SATA_PORTS 6
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/* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
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* BIOS will read it and start S3 resume at POST Entry */
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static void pc_cmos_set_s3_resume(void *opaque, int irq, int level)
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{
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ISADevice *s = opaque;
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if (level) {
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rtc_set_memory(s, 0xF, 0xFE);
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}
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}
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/* PC hardware initialisation */
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static void pc_q35_init(QEMUMachineInitArgs *args)
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{
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ram_addr_t ram_size = args->ram_size;
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const char *cpu_model = args->cpu_model;
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const char *kernel_filename = args->kernel_filename;
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const char *kernel_cmdline = args->kernel_cmdline;
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const char *initrd_filename = args->initrd_filename;
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const char *boot_device = args->boot_device;
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ram_addr_t below_4g_mem_size, above_4g_mem_size;
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Q35PCIHost *q35_host;
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PCIBus *host_bus;
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PCIDevice *lpc;
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BusState *idebus[MAX_SATA_PORTS];
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ISADevice *rtc_state;
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ISADevice *floppy;
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MemoryRegion *pci_memory;
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MemoryRegion *rom_memory;
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MemoryRegion *ram_memory;
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GSIState *gsi_state;
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ISABus *isa_bus;
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int pci_enabled = 1;
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qemu_irq *cpu_irq;
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qemu_irq *gsi;
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qemu_irq *i8259;
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int i;
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ICH9LPCState *ich9_lpc;
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PCIDevice *ahci;
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qemu_irq *cmos_s3;
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pc_cpus_init(cpu_model);
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kvmclock_create();
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if (ram_size >= 0xb0000000) {
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above_4g_mem_size = ram_size - 0xb0000000;
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below_4g_mem_size = 0xb0000000;
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} else {
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above_4g_mem_size = 0;
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below_4g_mem_size = ram_size;
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}
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/* pci enabled */
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if (pci_enabled) {
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pci_memory = g_new(MemoryRegion, 1);
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memory_region_init(pci_memory, "pci", INT64_MAX);
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rom_memory = pci_memory;
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} else {
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pci_memory = NULL;
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rom_memory = get_system_memory();
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}
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/* allocate ram and load rom/bios */
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if (!xen_enabled()) {
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pc_memory_init(get_system_memory(), kernel_filename, kernel_cmdline,
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initrd_filename, below_4g_mem_size, above_4g_mem_size,
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rom_memory, &ram_memory);
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}
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/* irq lines */
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gsi_state = g_malloc0(sizeof(*gsi_state));
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if (kvm_irqchip_in_kernel()) {
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kvm_pc_setup_irq_routing(pci_enabled);
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gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state,
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GSI_NUM_PINS);
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} else {
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gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
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}
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/* create pci host bus */
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q35_host = Q35_HOST_DEVICE(qdev_create(NULL, TYPE_Q35_HOST_DEVICE));
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q35_host->mch.ram_memory = ram_memory;
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q35_host->mch.pci_address_space = pci_memory;
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q35_host->mch.system_memory = get_system_memory();
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q35_host->mch.address_space_io = get_system_io();;
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q35_host->mch.below_4g_mem_size = below_4g_mem_size;
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q35_host->mch.above_4g_mem_size = above_4g_mem_size;
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/* pci */
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qdev_init_nofail(DEVICE(q35_host));
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host_bus = q35_host->host.pci.bus;
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/* create ISA bus */
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lpc = pci_create_simple_multifunction(host_bus, PCI_DEVFN(ICH9_LPC_DEV,
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ICH9_LPC_FUNC), true,
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TYPE_ICH9_LPC_DEVICE);
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ich9_lpc = ICH9_LPC_DEVICE(lpc);
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ich9_lpc->pic = gsi;
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ich9_lpc->ioapic = gsi_state->ioapic_irq;
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pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc,
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ICH9_LPC_NB_PIRQS);
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isa_bus = ich9_lpc->isa_bus;
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/*end early*/
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isa_bus_irqs(isa_bus, gsi);
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if (kvm_irqchip_in_kernel()) {
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i8259 = kvm_i8259_init(isa_bus);
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} else if (xen_enabled()) {
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i8259 = xen_interrupt_controller_init();
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} else {
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cpu_irq = pc_allocate_cpu_irq();
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i8259 = i8259_init(isa_bus, cpu_irq[0]);
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}
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for (i = 0; i < ISA_NUM_IRQS; i++) {
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gsi_state->i8259_irq[i] = i8259[i];
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}
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if (pci_enabled) {
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ioapic_init_gsi(gsi_state, NULL);
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}
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pc_register_ferr_irq(gsi[13]);
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/* init basic PC hardware */
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pc_basic_device_init(isa_bus, gsi, &rtc_state, &floppy, false);
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/* connect pm stuff to lpc */
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cmos_s3 = qemu_allocate_irqs(pc_cmos_set_s3_resume, rtc_state, 1);
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ich9_lpc_pm_init(lpc, *cmos_s3);
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/* ahci and SATA device, for q35 1 ahci controller is built-in */
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ahci = pci_create_simple_multifunction(host_bus,
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PCI_DEVFN(ICH9_SATA1_DEV,
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ICH9_SATA1_FUNC),
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true, "ich9-ahci");
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idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0");
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idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1");
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if (usb_enabled(false)) {
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/* Should we create 6 UHCI according to ich9 spec? */
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ehci_create_ich9_with_companions(host_bus, 0x1d);
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}
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/* TODO: Populate SPD eeprom data. */
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smbus_eeprom_init(ich9_smb_init(host_bus,
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PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC),
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0xb100),
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8, NULL, 0);
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pc_cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device,
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floppy, idebus[0], idebus[1], rtc_state);
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/* the rest devices to which pci devfn is automatically assigned */
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pc_vga_init(isa_bus, host_bus);
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audio_init(isa_bus, host_bus);
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pc_nic_init(isa_bus, host_bus);
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if (pci_enabled) {
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pc_pci_device_init(host_bus);
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}
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}
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static QEMUMachine pc_q35_machine = {
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.name = "q35-next",
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.alias = "q35",
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.desc = "Q35 chipset PC",
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.init = pc_q35_init,
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.max_cpus = 255,
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};
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static void pc_q35_machine_init(void)
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{
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qemu_register_machine(&pc_q35_machine);
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}
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machine_init(pc_q35_machine_init);
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