52d324ff13
Fix a typo in the host endianness macro and add a simple test to detect
regressions.
Fixes: 9bb0048ec6 ("target/ppc: convert xxspltw to vector operations")
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220310172047.61094-1-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
47 lines
2.0 KiB
C
47 lines
2.0 KiB
C
#include <stdio.h>
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#include <stdint.h>
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#include <inttypes.h>
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#include <assert.h>
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#define WORD_A 0xAAAAAAAAUL
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#define WORD_B 0xBBBBBBBBUL
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#define WORD_C 0xCCCCCCCCUL
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#define WORD_D 0xDDDDDDDDUL
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#define DWORD_HI (WORD_A << 32 | WORD_B)
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#define DWORD_LO (WORD_C << 32 | WORD_D)
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#define TEST(HI, LO, UIM, RES) \
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do { \
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union { \
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uint64_t u; \
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double f; \
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} h = { .u = HI }, l = { .u = LO }; \
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/* \
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* Use a pair of FPRs to load the VSR avoiding insns \
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* newer than xxswapd. \
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*/ \
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asm("xxmrghd 32, %0, %1\n\t" \
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"xxspltw 32, 32, %2\n\t" \
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"xxmrghd %0, 32, %0\n\t" \
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"xxswapd 32, 32\n\t" \
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"xxmrghd %1, 32, %1\n\t" \
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: "+f" (h.f), "+f" (l.f) \
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: "i" (UIM) \
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: "v0"); \
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printf("xxspltw(0x%016" PRIx64 "%016" PRIx64 ", %d) =" \
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" %016" PRIx64 "%016" PRIx64 "\n", HI, LO, UIM, \
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h.u, l.u); \
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assert(h.u == (RES)); \
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assert(l.u == (RES)); \
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} while (0)
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int main(void)
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{
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TEST(DWORD_HI, DWORD_LO, 0, WORD_A << 32 | WORD_A);
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TEST(DWORD_HI, DWORD_LO, 1, WORD_B << 32 | WORD_B);
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TEST(DWORD_HI, DWORD_LO, 2, WORD_C << 32 | WORD_C);
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TEST(DWORD_HI, DWORD_LO, 3, WORD_D << 32 | WORD_D);
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return 0;
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}
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