83 lines
1.8 KiB
C
83 lines
1.8 KiB
C
#ifndef E2K_CPU_H
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#define E2K_CPU_H
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#include "qemu/bswap.h"
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#include "cpu-qom.h"
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#include "exec/cpu-defs.h"
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void e2k_tcg_initialize(void);
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#define MMU_USER_IDX 1
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#define CPU_RESOLVING_TYPE TYPE_E2K_CPU
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struct e2k_def_t {
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const char *name;
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uint32_t isa_version;
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};
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typedef struct {
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/* register file */
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CPU_QuadU gregs[32]; /* general registers */
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CPU_QuadU pregs[224]; /* procedure regs, access through wreg */
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uint8_t greg_tags[32];
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uint8_t preg_tags[224];
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/* control registers */
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target_ulong ctpr1; // Control Transfer Preparation Register (CTPR)
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target_ulong ctpr2;
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target_ulong ctpr3;
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/* special registers */
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target_ulong *wreg; /* pointer to current window */
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uint32_t br; /* base rsegister offset, max 128 */
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target_ulong ip, nip; /* instruction address, next instruction address */
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uint32_t pfpfr; // Packed Floating Point Flag Register (PFPFR)
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uint32_t fpcr; // Floating point control register (FPCR)
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uint32_t fpsr; // Floating point state register (FPSR)
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int interrupt_index;
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/* Fields up to this point are cleared by a CPU reset */
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struct {} end_reset_fields;
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uint32_t version;
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struct e2k_def_t def;
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} CPUE2KState;
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/**
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* E2KCPU:
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* @env: #CPUE2KState
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*
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* An Elbrus CPU.
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*/
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struct E2KCPU {
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/*< private >*/
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CPUState parent_obj;
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/*< public >*/
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CPUNegativeOffsetState neg;
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CPUE2KState env;
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};
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static inline void cpu_get_tb_cpu_state(CPUE2KState *env, target_ulong *pc,
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target_ulong *cs_base, uint32_t *pflags)
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{
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*pc = env->ip;
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*cs_base = env->nip;
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*pflags = MMU_USER_IDX;
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}
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int e2k_cpu_signal_handler(int host_signum, void *pinfo, void *puc);
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#define cpu_signal_handler e2k_cpu_signal_handler
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typedef CPUE2KState CPUArchState;
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typedef E2KCPU ArchCPU;
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#include "exec/cpu-all.h"
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#endif
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