qemu-e2k/target
Richard Henderson 037c13c590 target/arm: Implement the ARMv8.1-HPD extension
Since the TCR_*.HPD bits were RES0 in ARMv8.0, we can simply
interpret the bits as if ARMv8.1-HPD is present without checking.
We will need a slightly different check for hpd for aarch32.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181203203839.757-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-12-13 14:41:24 +00:00
..
alpha vmstate: constify VMStateField 2018-11-27 15:35:15 +01:00
arm target/arm: Implement the ARMv8.1-HPD extension 2018-12-13 14:41:24 +00:00
cris target/cris/translate: Get rid of qemu_log_separate() 2018-10-16 17:57:23 +02:00
hppa vmstate: constify VMStateField 2018-11-27 15:35:15 +01:00
i386 x86 queue, 2018-12-11 2018-12-12 21:11:49 +00:00
lm32 tcg-next queue 2018-06-04 11:28:31 +01:00
m68k target/m68k: use EXCP_ILLEGAL instead of EXCP_UNSUPPORTED 2018-11-01 12:12:24 +01:00
microblaze target-microblaze: Rework NOP/zero instruction handling 2018-06-15 09:05:00 +02:00
mips vmstate: constify VMStateField 2018-11-27 15:35:15 +01:00
moxie tcg-next queue 2018-06-04 11:28:31 +01:00
nios2 tcg-next queue 2018-06-04 11:28:31 +01:00
openrisc vmstate: constify VMStateField 2018-11-27 15:35:15 +01:00
ppc vmstate: constify VMStateField 2018-11-27 15:35:15 +01:00
riscv RISC-V: Respect fences for user-only emulators 2018-11-13 15:12:15 -08:00
s390x target/s390x: Check HAVE_ATOMIC128 and HAVE_CMPXCHG128 at translate 2018-10-18 19:46:53 -07:00
sh4 sh4: fix use_icount with linux-user 2018-08-20 00:11:06 +02:00
sparc vmstate: constify VMStateField 2018-11-27 15:35:15 +01:00
tilegx tcg-next queue 2018-06-04 11:28:31 +01:00
tricore tcg: Pass tb and index to tcg_gen_exit_tb separately 2018-06-01 15:15:27 -07:00
unicore32 target/unicore32: remove tlb_flush from uc32_init_fn 2018-10-18 18:58:10 -07:00
xtensa target/xtensa: drop num_[core_]regs from dc232b/dc233c configs 2018-11-20 12:20:41 -08:00