Bin Meng 0694dabe97 hw/ssi: Add SiFive SPI controller support ... This adds the SiFive SPI controller model for the FU540 SoC. The direct memory-mapped SPI flash mode is unsupported. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210126060007.12904-4-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2021-03-04 09:43:29 -05:00
..
aspeed_smc.c	hw/ssi/aspeed_smc: Rename 'max_slaves' variable as 'max_peripherals'	2020-12-10 12:15:03 -05:00
imx_spi.c	hw/ssi: imx_spi: Correct tx and rx fifo endianness	2021-02-02 17:00:55 +00:00
Kconfig	hw/ssi: Add SiFive SPI controller support	2021-03-04 09:43:29 -05:00
meson.build	hw/ssi: Add SiFive SPI controller support	2021-03-04 09:43:29 -05:00
mss-spi.c
npcm7xx_fiu.c	hw/*: Use type casting for SysBusDevice in NPCM7XX	2021-01-12 21:19:02 +00:00
omap_spi.c
pl022.c	hw/ssi: Rename SSI 'slave' as 'peripheral'	2020-12-10 12:15:03 -05:00
sifive_spi.c	hw/ssi: Add SiFive SPI controller support	2021-03-04 09:43:29 -05:00
ssi.c	hw/ssi: Rename SSI 'slave' as 'peripheral'	2020-12-10 12:15:03 -05:00
stm32f2xx_spi.c
trace-events	hw/ssi/npcm7xx_fiu: Fix handling of unsigned integer	2020-10-08 15:24:32 +01:00
trace.h	trace: switch position of headers to what Meson requires	2020-08-21 06:18:24 -04:00
xilinx_spi.c	ssi: Fix bad printf format specifiers	2020-11-10 11:03:47 +00:00
xilinx_spips.c	hw/core/stream: Rename StreamSlave as StreamSink	2020-12-10 12:15:04 -05:00