72 lines
1.7 KiB
C
72 lines
1.7 KiB
C
/*
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* QEMU RISC-V VirtIO machine interface
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*
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* Copyright (c) 2017 SiFive, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_RISCV_VIRT_H
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#define HW_RISCV_VIRT_H
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typedef struct {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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RISCVHartArrayState soc;
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DeviceState *plic;
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void *fdt;
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int fdt_size;
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} RISCVVirtState;
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enum {
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VIRT_DEBUG,
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VIRT_MROM,
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VIRT_TEST,
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VIRT_CLINT,
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VIRT_PLIC,
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VIRT_UART0,
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VIRT_VIRTIO,
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VIRT_DRAM
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};
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enum {
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UART0_IRQ = 10,
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VIRTIO_IRQ = 1, /* 1 to 8 */
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VIRTIO_COUNT = 8,
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VIRTIO_NDEV = 10
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};
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enum {
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VIRT_CLOCK_FREQ = 1000000000
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};
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#define VIRT_PLIC_HART_CONFIG "MS"
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#define VIRT_PLIC_NUM_SOURCES 127
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#define VIRT_PLIC_NUM_PRIORITIES 7
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#define VIRT_PLIC_PRIORITY_BASE 0x0
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#define VIRT_PLIC_PENDING_BASE 0x1000
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#define VIRT_PLIC_ENABLE_BASE 0x2000
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#define VIRT_PLIC_ENABLE_STRIDE 0x80
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#define VIRT_PLIC_CONTEXT_BASE 0x200000
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#define VIRT_PLIC_CONTEXT_STRIDE 0x1000
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#if defined(TARGET_RISCV32)
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#define VIRT_CPU TYPE_RISCV_CPU_RV32GCSU_V1_10_0
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#elif defined(TARGET_RISCV64)
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#define VIRT_CPU TYPE_RISCV_CPU_RV64GCSU_V1_10_0
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#endif
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#endif
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