349 lines
8.6 KiB
C
349 lines
8.6 KiB
C
/*
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* QEMU IDE Emulation: MacIO support.
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*
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* Copyright (c) 2003 Fabrice Bellard
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* Copyright (c) 2006 Openedhand Ltd.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <hw/hw.h>
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#include <hw/ppc_mac.h>
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#include <hw/mac_dbdma.h>
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#include "block.h"
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#include "dma.h"
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#include <hw/ide/internal.h>
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/***********************************************************/
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/* MacIO based PowerPC IDE */
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typedef struct MACIOIDEState {
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MemoryRegion mem;
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IDEBus bus;
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BlockDriverAIOCB *aiocb;
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} MACIOIDEState;
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#define MACIO_PAGE_SIZE 4096
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static void pmac_ide_atapi_transfer_cb(void *opaque, int ret)
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{
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DBDMA_io *io = opaque;
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MACIOIDEState *m = io->opaque;
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IDEState *s = idebus_active_if(&m->bus);
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if (ret < 0) {
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m->aiocb = NULL;
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qemu_sglist_destroy(&s->sg);
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ide_atapi_io_error(s, ret);
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goto done;
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}
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if (s->io_buffer_size > 0) {
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m->aiocb = NULL;
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qemu_sglist_destroy(&s->sg);
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s->packet_transfer_size -= s->io_buffer_size;
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s->io_buffer_index += s->io_buffer_size;
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s->lba += s->io_buffer_index >> 11;
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s->io_buffer_index &= 0x7ff;
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}
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if (s->packet_transfer_size <= 0)
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ide_atapi_cmd_ok(s);
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if (io->len == 0) {
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goto done;
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}
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/* launch next transfer */
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s->io_buffer_size = io->len;
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qemu_sglist_init(&s->sg, io->len / MACIO_PAGE_SIZE + 1, NULL);
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qemu_sglist_add(&s->sg, io->addr, io->len);
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io->addr += io->len;
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io->len = 0;
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m->aiocb = dma_bdrv_read(s->bs, &s->sg,
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(int64_t)(s->lba << 2) + (s->io_buffer_index >> 9),
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pmac_ide_atapi_transfer_cb, io);
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return;
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done:
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bdrv_acct_done(s->bs, &s->acct);
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io->dma_end(opaque);
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}
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static void pmac_ide_transfer_cb(void *opaque, int ret)
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{
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DBDMA_io *io = opaque;
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MACIOIDEState *m = io->opaque;
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IDEState *s = idebus_active_if(&m->bus);
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int n;
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int64_t sector_num;
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if (ret < 0) {
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m->aiocb = NULL;
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qemu_sglist_destroy(&s->sg);
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ide_dma_error(s);
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goto done;
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}
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sector_num = ide_get_sector(s);
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if (s->io_buffer_size > 0) {
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m->aiocb = NULL;
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qemu_sglist_destroy(&s->sg);
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n = (s->io_buffer_size + 0x1ff) >> 9;
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sector_num += n;
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ide_set_sector(s, sector_num);
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s->nsector -= n;
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}
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/* end of transfer ? */
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if (s->nsector == 0) {
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s->status = READY_STAT | SEEK_STAT;
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ide_set_irq(s->bus);
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}
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/* end of DMA ? */
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if (io->len == 0) {
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goto done;
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}
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/* launch next transfer */
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s->io_buffer_index = 0;
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s->io_buffer_size = io->len;
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qemu_sglist_init(&s->sg, io->len / MACIO_PAGE_SIZE + 1, NULL);
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qemu_sglist_add(&s->sg, io->addr, io->len);
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io->addr += io->len;
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io->len = 0;
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switch (s->dma_cmd) {
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case IDE_DMA_READ:
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m->aiocb = dma_bdrv_read(s->bs, &s->sg, sector_num,
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pmac_ide_transfer_cb, io);
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break;
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case IDE_DMA_WRITE:
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m->aiocb = dma_bdrv_write(s->bs, &s->sg, sector_num,
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pmac_ide_transfer_cb, io);
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break;
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case IDE_DMA_TRIM:
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m->aiocb = dma_bdrv_io(s->bs, &s->sg, sector_num,
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ide_issue_trim, pmac_ide_transfer_cb, s,
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DMA_DIRECTION_TO_DEVICE);
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break;
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}
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return;
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done:
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if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) {
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bdrv_acct_done(s->bs, &s->acct);
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}
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io->dma_end(io);
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}
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static void pmac_ide_transfer(DBDMA_io *io)
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{
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MACIOIDEState *m = io->opaque;
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IDEState *s = idebus_active_if(&m->bus);
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s->io_buffer_size = 0;
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if (s->drive_kind == IDE_CD) {
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bdrv_acct_start(s->bs, &s->acct, io->len, BDRV_ACCT_READ);
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pmac_ide_atapi_transfer_cb(io, 0);
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return;
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}
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switch (s->dma_cmd) {
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case IDE_DMA_READ:
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bdrv_acct_start(s->bs, &s->acct, io->len, BDRV_ACCT_READ);
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break;
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case IDE_DMA_WRITE:
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bdrv_acct_start(s->bs, &s->acct, io->len, BDRV_ACCT_WRITE);
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break;
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default:
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break;
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}
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pmac_ide_transfer_cb(io, 0);
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}
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static void pmac_ide_flush(DBDMA_io *io)
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{
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MACIOIDEState *m = io->opaque;
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if (m->aiocb) {
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bdrv_drain_all();
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}
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}
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/* PowerMac IDE memory IO */
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static void pmac_ide_writeb (void *opaque,
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target_phys_addr_t addr, uint32_t val)
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{
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MACIOIDEState *d = opaque;
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addr = (addr & 0xFFF) >> 4;
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switch (addr) {
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case 1 ... 7:
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ide_ioport_write(&d->bus, addr, val);
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break;
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case 8:
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case 22:
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ide_cmd_write(&d->bus, 0, val);
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break;
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default:
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break;
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}
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}
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static uint32_t pmac_ide_readb (void *opaque,target_phys_addr_t addr)
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{
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uint8_t retval;
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MACIOIDEState *d = opaque;
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addr = (addr & 0xFFF) >> 4;
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switch (addr) {
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case 1 ... 7:
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retval = ide_ioport_read(&d->bus, addr);
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break;
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case 8:
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case 22:
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retval = ide_status_read(&d->bus, 0);
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break;
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default:
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retval = 0xFF;
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break;
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}
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return retval;
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}
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static void pmac_ide_writew (void *opaque,
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target_phys_addr_t addr, uint32_t val)
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{
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MACIOIDEState *d = opaque;
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addr = (addr & 0xFFF) >> 4;
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val = bswap16(val);
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if (addr == 0) {
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ide_data_writew(&d->bus, 0, val);
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}
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}
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static uint32_t pmac_ide_readw (void *opaque,target_phys_addr_t addr)
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{
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uint16_t retval;
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MACIOIDEState *d = opaque;
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addr = (addr & 0xFFF) >> 4;
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if (addr == 0) {
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retval = ide_data_readw(&d->bus, 0);
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} else {
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retval = 0xFFFF;
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}
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retval = bswap16(retval);
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return retval;
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}
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static void pmac_ide_writel (void *opaque,
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target_phys_addr_t addr, uint32_t val)
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{
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MACIOIDEState *d = opaque;
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addr = (addr & 0xFFF) >> 4;
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val = bswap32(val);
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if (addr == 0) {
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ide_data_writel(&d->bus, 0, val);
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}
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}
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static uint32_t pmac_ide_readl (void *opaque,target_phys_addr_t addr)
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{
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uint32_t retval;
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MACIOIDEState *d = opaque;
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addr = (addr & 0xFFF) >> 4;
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if (addr == 0) {
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retval = ide_data_readl(&d->bus, 0);
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} else {
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retval = 0xFFFFFFFF;
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}
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retval = bswap32(retval);
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return retval;
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}
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static const MemoryRegionOps pmac_ide_ops = {
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.old_mmio = {
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.write = {
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pmac_ide_writeb,
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pmac_ide_writew,
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pmac_ide_writel,
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},
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.read = {
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pmac_ide_readb,
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pmac_ide_readw,
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pmac_ide_readl,
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},
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},
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static const VMStateDescription vmstate_pmac = {
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.name = "ide",
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.version_id = 3,
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.minimum_version_id = 0,
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.minimum_version_id_old = 0,
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.fields = (VMStateField []) {
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VMSTATE_IDE_BUS(bus, MACIOIDEState),
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VMSTATE_IDE_DRIVES(bus.ifs, MACIOIDEState),
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VMSTATE_END_OF_LIST()
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}
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};
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static void pmac_ide_reset(void *opaque)
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{
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MACIOIDEState *d = opaque;
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ide_bus_reset(&d->bus);
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}
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/* hd_table must contain 4 block drivers */
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/* PowerMac uses memory mapped registers, not I/O. Return the memory
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I/O index to access the ide. */
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MemoryRegion *pmac_ide_init (DriveInfo **hd_table, qemu_irq irq,
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void *dbdma, int channel, qemu_irq dma_irq)
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{
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MACIOIDEState *d;
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d = g_malloc0(sizeof(MACIOIDEState));
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ide_init2_with_non_qdev_drives(&d->bus, hd_table[0], hd_table[1], irq);
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if (dbdma)
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DBDMA_register_channel(dbdma, channel, dma_irq, pmac_ide_transfer, pmac_ide_flush, d);
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memory_region_init_io(&d->mem, &pmac_ide_ops, d, "pmac-ide", 0x1000);
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vmstate_register(NULL, 0, &vmstate_pmac, d);
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qemu_register_reset(pmac_ide_reset, d);
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return &d->mem;
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}
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