721 lines
29 KiB
C
721 lines
29 KiB
C
/*
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* emulator main execution loop
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "config.h"
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#include "cpu.h"
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#include "disas/disas.h"
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#include "tcg.h"
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#include "qemu/atomic.h"
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#include "sysemu/qtest.h"
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bool qemu_cpu_has_work(CPUState *cpu)
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{
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return cpu_has_work(cpu);
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}
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void cpu_loop_exit(CPUArchState *env)
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{
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CPUState *cpu = ENV_GET_CPU(env);
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cpu->current_tb = NULL;
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siglongjmp(env->jmp_env, 1);
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}
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/* exit the current TB from a signal handler. The host registers are
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restored in a state compatible with the CPU emulator
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*/
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#if defined(CONFIG_SOFTMMU)
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void cpu_resume_from_signal(CPUArchState *env, void *puc)
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{
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/* XXX: restore cpu registers saved in host registers */
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env->exception_index = -1;
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siglongjmp(env->jmp_env, 1);
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}
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#endif
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/* Execute a TB, and fix up the CPU state afterwards if necessary */
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static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, uint8_t *tb_ptr)
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{
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CPUArchState *env = cpu->env_ptr;
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tcg_target_ulong next_tb = tcg_qemu_tb_exec(env, tb_ptr);
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if ((next_tb & TB_EXIT_MASK) > TB_EXIT_IDX1) {
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/* We didn't start executing this TB (eg because the instruction
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* counter hit zero); we must restore the guest PC to the address
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* of the start of the TB.
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*/
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CPUClass *cc = CPU_GET_CLASS(cpu);
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TranslationBlock *tb = (TranslationBlock *)(next_tb & ~TB_EXIT_MASK);
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if (cc->synchronize_from_tb) {
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cc->synchronize_from_tb(cpu, tb);
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} else {
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assert(cc->set_pc);
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cc->set_pc(cpu, tb->pc);
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}
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}
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if ((next_tb & TB_EXIT_MASK) == TB_EXIT_REQUESTED) {
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/* We were asked to stop executing TBs (probably a pending
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* interrupt. We've now stopped, so clear the flag.
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*/
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cpu->tcg_exit_req = 0;
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}
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return next_tb;
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}
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/* Execute the code without caching the generated code. An interpreter
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could be used if available. */
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static void cpu_exec_nocache(CPUArchState *env, int max_cycles,
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TranslationBlock *orig_tb)
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{
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CPUState *cpu = ENV_GET_CPU(env);
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TranslationBlock *tb;
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/* Should never happen.
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We only end up here when an existing TB is too long. */
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if (max_cycles > CF_COUNT_MASK)
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max_cycles = CF_COUNT_MASK;
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tb = tb_gen_code(env, orig_tb->pc, orig_tb->cs_base, orig_tb->flags,
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max_cycles);
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cpu->current_tb = tb;
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/* execute the generated code */
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cpu_tb_exec(cpu, tb->tc_ptr);
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cpu->current_tb = NULL;
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tb_phys_invalidate(tb, -1);
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tb_free(tb);
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}
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static TranslationBlock *tb_find_slow(CPUArchState *env,
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target_ulong pc,
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target_ulong cs_base,
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uint64_t flags)
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{
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TranslationBlock *tb, **ptb1;
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unsigned int h;
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tb_page_addr_t phys_pc, phys_page1;
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target_ulong virt_page2;
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tcg_ctx.tb_ctx.tb_invalidated_flag = 0;
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/* find translated block using physical mappings */
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phys_pc = get_page_addr_code(env, pc);
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phys_page1 = phys_pc & TARGET_PAGE_MASK;
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h = tb_phys_hash_func(phys_pc);
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ptb1 = &tcg_ctx.tb_ctx.tb_phys_hash[h];
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for(;;) {
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tb = *ptb1;
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if (!tb)
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goto not_found;
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if (tb->pc == pc &&
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tb->page_addr[0] == phys_page1 &&
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tb->cs_base == cs_base &&
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tb->flags == flags) {
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/* check next page if needed */
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if (tb->page_addr[1] != -1) {
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tb_page_addr_t phys_page2;
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virt_page2 = (pc & TARGET_PAGE_MASK) +
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TARGET_PAGE_SIZE;
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phys_page2 = get_page_addr_code(env, virt_page2);
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if (tb->page_addr[1] == phys_page2)
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goto found;
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} else {
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goto found;
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}
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}
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ptb1 = &tb->phys_hash_next;
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}
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not_found:
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/* if no translated code available, then translate it now */
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tb = tb_gen_code(env, pc, cs_base, flags, 0);
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found:
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/* Move the last found TB to the head of the list */
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if (likely(*ptb1)) {
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*ptb1 = tb->phys_hash_next;
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tb->phys_hash_next = tcg_ctx.tb_ctx.tb_phys_hash[h];
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tcg_ctx.tb_ctx.tb_phys_hash[h] = tb;
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}
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/* we add the TB in the virtual pc hash table */
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env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
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return tb;
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}
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static inline TranslationBlock *tb_find_fast(CPUArchState *env)
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{
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TranslationBlock *tb;
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target_ulong cs_base, pc;
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int flags;
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/* we record a subset of the CPU state. It will
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always be the same before a given translated block
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is executed. */
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cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
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tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
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if (unlikely(!tb || tb->pc != pc || tb->cs_base != cs_base ||
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tb->flags != flags)) {
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tb = tb_find_slow(env, pc, cs_base, flags);
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}
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return tb;
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}
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static CPUDebugExcpHandler *debug_excp_handler;
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void cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler)
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{
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debug_excp_handler = handler;
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}
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static void cpu_handle_debug_exception(CPUArchState *env)
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{
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CPUWatchpoint *wp;
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if (!env->watchpoint_hit) {
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QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
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wp->flags &= ~BP_WATCHPOINT_HIT;
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}
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}
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if (debug_excp_handler) {
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debug_excp_handler(env);
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}
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}
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/* main execution loop */
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volatile sig_atomic_t exit_request;
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int cpu_exec(CPUArchState *env)
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{
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CPUState *cpu = ENV_GET_CPU(env);
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#if !(defined(CONFIG_USER_ONLY) && \
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(defined(TARGET_M68K) || defined(TARGET_PPC) || defined(TARGET_S390X)))
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CPUClass *cc = CPU_GET_CLASS(cpu);
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#endif
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int ret, interrupt_request;
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TranslationBlock *tb;
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uint8_t *tc_ptr;
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tcg_target_ulong next_tb;
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if (cpu->halted) {
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if (!cpu_has_work(cpu)) {
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return EXCP_HALTED;
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}
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cpu->halted = 0;
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}
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current_cpu = cpu;
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/* As long as current_cpu is null, up to the assignment just above,
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* requests by other threads to exit the execution loop are expected to
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* be issued using the exit_request global. We must make sure that our
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* evaluation of the global value is performed past the current_cpu
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* value transition point, which requires a memory barrier as well as
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* an instruction scheduling constraint on modern architectures. */
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smp_mb();
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if (unlikely(exit_request)) {
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cpu->exit_request = 1;
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}
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#if defined(TARGET_I386)
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/* put eflags in CPU temporary format */
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CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
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env->df = 1 - (2 * ((env->eflags >> 10) & 1));
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CC_OP = CC_OP_EFLAGS;
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env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
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#elif defined(TARGET_SPARC)
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#elif defined(TARGET_M68K)
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env->cc_op = CC_OP_FLAGS;
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env->cc_dest = env->sr & 0xf;
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env->cc_x = (env->sr >> 4) & 1;
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#elif defined(TARGET_ALPHA)
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#elif defined(TARGET_ARM)
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#elif defined(TARGET_UNICORE32)
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#elif defined(TARGET_PPC)
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env->reserve_addr = -1;
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#elif defined(TARGET_LM32)
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#elif defined(TARGET_MICROBLAZE)
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#elif defined(TARGET_MIPS)
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#elif defined(TARGET_MOXIE)
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#elif defined(TARGET_OPENRISC)
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#elif defined(TARGET_SH4)
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#elif defined(TARGET_CRIS)
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#elif defined(TARGET_S390X)
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#elif defined(TARGET_XTENSA)
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/* XXXXX */
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#else
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#error unsupported target CPU
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#endif
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env->exception_index = -1;
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/* prepare setjmp context for exception handling */
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for(;;) {
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if (sigsetjmp(env->jmp_env, 0) == 0) {
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/* if an exception is pending, we execute it here */
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if (env->exception_index >= 0) {
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if (env->exception_index >= EXCP_INTERRUPT) {
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/* exit request from the cpu execution loop */
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ret = env->exception_index;
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if (ret == EXCP_DEBUG) {
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cpu_handle_debug_exception(env);
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}
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break;
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} else {
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#if defined(CONFIG_USER_ONLY)
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/* if user mode only, we simulate a fake exception
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which will be handled outside the cpu execution
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loop */
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#if defined(TARGET_I386)
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cc->do_interrupt(cpu);
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#endif
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ret = env->exception_index;
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break;
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#else
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cc->do_interrupt(cpu);
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env->exception_index = -1;
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#endif
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}
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}
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next_tb = 0; /* force lookup of first TB */
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for(;;) {
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interrupt_request = cpu->interrupt_request;
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if (unlikely(interrupt_request)) {
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if (unlikely(cpu->singlestep_enabled & SSTEP_NOIRQ)) {
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/* Mask out external interrupts for this step. */
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interrupt_request &= ~CPU_INTERRUPT_SSTEP_MASK;
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}
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if (interrupt_request & CPU_INTERRUPT_DEBUG) {
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cpu->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
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env->exception_index = EXCP_DEBUG;
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cpu_loop_exit(env);
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}
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#if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
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defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) || \
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defined(TARGET_MICROBLAZE) || defined(TARGET_LM32) || defined(TARGET_UNICORE32)
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if (interrupt_request & CPU_INTERRUPT_HALT) {
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cpu->interrupt_request &= ~CPU_INTERRUPT_HALT;
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cpu->halted = 1;
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env->exception_index = EXCP_HLT;
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cpu_loop_exit(env);
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}
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#endif
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#if defined(TARGET_I386)
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#if !defined(CONFIG_USER_ONLY)
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if (interrupt_request & CPU_INTERRUPT_POLL) {
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cpu->interrupt_request &= ~CPU_INTERRUPT_POLL;
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apic_poll_irq(env->apic_state);
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}
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#endif
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if (interrupt_request & CPU_INTERRUPT_INIT) {
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cpu_svm_check_intercept_param(env, SVM_EXIT_INIT,
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0);
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do_cpu_init(x86_env_get_cpu(env));
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env->exception_index = EXCP_HALTED;
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cpu_loop_exit(env);
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} else if (interrupt_request & CPU_INTERRUPT_SIPI) {
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do_cpu_sipi(x86_env_get_cpu(env));
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} else if (env->hflags2 & HF2_GIF_MASK) {
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if ((interrupt_request & CPU_INTERRUPT_SMI) &&
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!(env->hflags & HF_SMM_MASK)) {
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cpu_svm_check_intercept_param(env, SVM_EXIT_SMI,
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0);
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cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
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do_smm_enter(x86_env_get_cpu(env));
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next_tb = 0;
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} else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
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!(env->hflags2 & HF2_NMI_MASK)) {
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cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
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env->hflags2 |= HF2_NMI_MASK;
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do_interrupt_x86_hardirq(env, EXCP02_NMI, 1);
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next_tb = 0;
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} else if (interrupt_request & CPU_INTERRUPT_MCE) {
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cpu->interrupt_request &= ~CPU_INTERRUPT_MCE;
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do_interrupt_x86_hardirq(env, EXCP12_MCHK, 0);
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next_tb = 0;
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} else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
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(((env->hflags2 & HF2_VINTR_MASK) &&
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(env->hflags2 & HF2_HIF_MASK)) ||
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(!(env->hflags2 & HF2_VINTR_MASK) &&
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(env->eflags & IF_MASK &&
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!(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
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int intno;
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cpu_svm_check_intercept_param(env, SVM_EXIT_INTR,
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0);
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cpu->interrupt_request &= ~(CPU_INTERRUPT_HARD |
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CPU_INTERRUPT_VIRQ);
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intno = cpu_get_pic_interrupt(env);
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qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing hardware INT=0x%02x\n", intno);
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do_interrupt_x86_hardirq(env, intno, 1);
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/* ensure that no TB jump will be modified as
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the program flow was changed */
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next_tb = 0;
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#if !defined(CONFIG_USER_ONLY)
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} else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
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(env->eflags & IF_MASK) &&
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!(env->hflags & HF_INHIBIT_IRQ_MASK)) {
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int intno;
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/* FIXME: this should respect TPR */
|
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cpu_svm_check_intercept_param(env, SVM_EXIT_VINTR,
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0);
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intno = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_vector));
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qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing virtual hardware INT=0x%02x\n", intno);
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do_interrupt_x86_hardirq(env, intno, 1);
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cpu->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
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next_tb = 0;
|
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#endif
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}
|
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}
|
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#elif defined(TARGET_PPC)
|
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if ((interrupt_request & CPU_INTERRUPT_RESET)) {
|
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cpu_reset(cpu);
|
|
}
|
|
if (interrupt_request & CPU_INTERRUPT_HARD) {
|
|
ppc_hw_interrupt(env);
|
|
if (env->pending_interrupts == 0) {
|
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cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
|
|
}
|
|
next_tb = 0;
|
|
}
|
|
#elif defined(TARGET_LM32)
|
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if ((interrupt_request & CPU_INTERRUPT_HARD)
|
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&& (env->ie & IE_IE)) {
|
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env->exception_index = EXCP_IRQ;
|
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cc->do_interrupt(cpu);
|
|
next_tb = 0;
|
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}
|
|
#elif defined(TARGET_MICROBLAZE)
|
|
if ((interrupt_request & CPU_INTERRUPT_HARD)
|
|
&& (env->sregs[SR_MSR] & MSR_IE)
|
|
&& !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP))
|
|
&& !(env->iflags & (D_FLAG | IMM_FLAG))) {
|
|
env->exception_index = EXCP_IRQ;
|
|
cc->do_interrupt(cpu);
|
|
next_tb = 0;
|
|
}
|
|
#elif defined(TARGET_MIPS)
|
|
if ((interrupt_request & CPU_INTERRUPT_HARD) &&
|
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cpu_mips_hw_interrupts_pending(env)) {
|
|
/* Raise it */
|
|
env->exception_index = EXCP_EXT_INTERRUPT;
|
|
env->error_code = 0;
|
|
cc->do_interrupt(cpu);
|
|
next_tb = 0;
|
|
}
|
|
#elif defined(TARGET_OPENRISC)
|
|
{
|
|
int idx = -1;
|
|
if ((interrupt_request & CPU_INTERRUPT_HARD)
|
|
&& (env->sr & SR_IEE)) {
|
|
idx = EXCP_INT;
|
|
}
|
|
if ((interrupt_request & CPU_INTERRUPT_TIMER)
|
|
&& (env->sr & SR_TEE)) {
|
|
idx = EXCP_TICK;
|
|
}
|
|
if (idx >= 0) {
|
|
env->exception_index = idx;
|
|
cc->do_interrupt(cpu);
|
|
next_tb = 0;
|
|
}
|
|
}
|
|
#elif defined(TARGET_SPARC)
|
|
if (interrupt_request & CPU_INTERRUPT_HARD) {
|
|
if (cpu_interrupts_enabled(env) &&
|
|
env->interrupt_index > 0) {
|
|
int pil = env->interrupt_index & 0xf;
|
|
int type = env->interrupt_index & 0xf0;
|
|
|
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if (((type == TT_EXTINT) &&
|
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cpu_pil_allowed(env, pil)) ||
|
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type != TT_EXTINT) {
|
|
env->exception_index = env->interrupt_index;
|
|
cc->do_interrupt(cpu);
|
|
next_tb = 0;
|
|
}
|
|
}
|
|
}
|
|
#elif defined(TARGET_ARM)
|
|
if (interrupt_request & CPU_INTERRUPT_FIQ
|
|
&& !(env->uncached_cpsr & CPSR_F)) {
|
|
env->exception_index = EXCP_FIQ;
|
|
cc->do_interrupt(cpu);
|
|
next_tb = 0;
|
|
}
|
|
/* ARMv7-M interrupt return works by loading a magic value
|
|
into the PC. On real hardware the load causes the
|
|
return to occur. The qemu implementation performs the
|
|
jump normally, then does the exception return when the
|
|
CPU tries to execute code at the magic address.
|
|
This will cause the magic PC value to be pushed to
|
|
the stack if an interrupt occurred at the wrong time.
|
|
We avoid this by disabling interrupts when
|
|
pc contains a magic address. */
|
|
if (interrupt_request & CPU_INTERRUPT_HARD
|
|
&& ((IS_M(env) && env->regs[15] < 0xfffffff0)
|
|
|| !(env->uncached_cpsr & CPSR_I))) {
|
|
env->exception_index = EXCP_IRQ;
|
|
cc->do_interrupt(cpu);
|
|
next_tb = 0;
|
|
}
|
|
#elif defined(TARGET_UNICORE32)
|
|
if (interrupt_request & CPU_INTERRUPT_HARD
|
|
&& !(env->uncached_asr & ASR_I)) {
|
|
env->exception_index = UC32_EXCP_INTR;
|
|
cc->do_interrupt(cpu);
|
|
next_tb = 0;
|
|
}
|
|
#elif defined(TARGET_SH4)
|
|
if (interrupt_request & CPU_INTERRUPT_HARD) {
|
|
cc->do_interrupt(cpu);
|
|
next_tb = 0;
|
|
}
|
|
#elif defined(TARGET_ALPHA)
|
|
{
|
|
int idx = -1;
|
|
/* ??? This hard-codes the OSF/1 interrupt levels. */
|
|
switch (env->pal_mode ? 7 : env->ps & PS_INT_MASK) {
|
|
case 0 ... 3:
|
|
if (interrupt_request & CPU_INTERRUPT_HARD) {
|
|
idx = EXCP_DEV_INTERRUPT;
|
|
}
|
|
/* FALLTHRU */
|
|
case 4:
|
|
if (interrupt_request & CPU_INTERRUPT_TIMER) {
|
|
idx = EXCP_CLK_INTERRUPT;
|
|
}
|
|
/* FALLTHRU */
|
|
case 5:
|
|
if (interrupt_request & CPU_INTERRUPT_SMP) {
|
|
idx = EXCP_SMP_INTERRUPT;
|
|
}
|
|
/* FALLTHRU */
|
|
case 6:
|
|
if (interrupt_request & CPU_INTERRUPT_MCHK) {
|
|
idx = EXCP_MCHK;
|
|
}
|
|
}
|
|
if (idx >= 0) {
|
|
env->exception_index = idx;
|
|
env->error_code = 0;
|
|
cc->do_interrupt(cpu);
|
|
next_tb = 0;
|
|
}
|
|
}
|
|
#elif defined(TARGET_CRIS)
|
|
if (interrupt_request & CPU_INTERRUPT_HARD
|
|
&& (env->pregs[PR_CCS] & I_FLAG)
|
|
&& !env->locked_irq) {
|
|
env->exception_index = EXCP_IRQ;
|
|
cc->do_interrupt(cpu);
|
|
next_tb = 0;
|
|
}
|
|
if (interrupt_request & CPU_INTERRUPT_NMI) {
|
|
unsigned int m_flag_archval;
|
|
if (env->pregs[PR_VR] < 32) {
|
|
m_flag_archval = M_FLAG_V10;
|
|
} else {
|
|
m_flag_archval = M_FLAG_V32;
|
|
}
|
|
if ((env->pregs[PR_CCS] & m_flag_archval)) {
|
|
env->exception_index = EXCP_NMI;
|
|
cc->do_interrupt(cpu);
|
|
next_tb = 0;
|
|
}
|
|
}
|
|
#elif defined(TARGET_M68K)
|
|
if (interrupt_request & CPU_INTERRUPT_HARD
|
|
&& ((env->sr & SR_I) >> SR_I_SHIFT)
|
|
< env->pending_level) {
|
|
/* Real hardware gets the interrupt vector via an
|
|
IACK cycle at this point. Current emulated
|
|
hardware doesn't rely on this, so we
|
|
provide/save the vector when the interrupt is
|
|
first signalled. */
|
|
env->exception_index = env->pending_vector;
|
|
do_interrupt_m68k_hardirq(env);
|
|
next_tb = 0;
|
|
}
|
|
#elif defined(TARGET_S390X) && !defined(CONFIG_USER_ONLY)
|
|
if ((interrupt_request & CPU_INTERRUPT_HARD) &&
|
|
(env->psw.mask & PSW_MASK_EXT)) {
|
|
cc->do_interrupt(cpu);
|
|
next_tb = 0;
|
|
}
|
|
#elif defined(TARGET_XTENSA)
|
|
if (interrupt_request & CPU_INTERRUPT_HARD) {
|
|
env->exception_index = EXC_IRQ;
|
|
cc->do_interrupt(cpu);
|
|
next_tb = 0;
|
|
}
|
|
#endif
|
|
/* Don't use the cached interrupt_request value,
|
|
do_interrupt may have updated the EXITTB flag. */
|
|
if (cpu->interrupt_request & CPU_INTERRUPT_EXITTB) {
|
|
cpu->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
|
|
/* ensure that no TB jump will be modified as
|
|
the program flow was changed */
|
|
next_tb = 0;
|
|
}
|
|
}
|
|
if (unlikely(cpu->exit_request)) {
|
|
cpu->exit_request = 0;
|
|
env->exception_index = EXCP_INTERRUPT;
|
|
cpu_loop_exit(env);
|
|
}
|
|
#if defined(DEBUG_DISAS)
|
|
if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
|
|
/* restore flags in standard format */
|
|
#if defined(TARGET_I386)
|
|
log_cpu_state(cpu, CPU_DUMP_CCOP);
|
|
#elif defined(TARGET_M68K)
|
|
cpu_m68k_flush_flags(env, env->cc_op);
|
|
env->cc_op = CC_OP_FLAGS;
|
|
env->sr = (env->sr & 0xffe0)
|
|
| env->cc_dest | (env->cc_x << 4);
|
|
log_cpu_state(cpu, 0);
|
|
#else
|
|
log_cpu_state(cpu, 0);
|
|
#endif
|
|
}
|
|
#endif /* DEBUG_DISAS */
|
|
spin_lock(&tcg_ctx.tb_ctx.tb_lock);
|
|
tb = tb_find_fast(env);
|
|
/* Note: we do it here to avoid a gcc bug on Mac OS X when
|
|
doing it in tb_find_slow */
|
|
if (tcg_ctx.tb_ctx.tb_invalidated_flag) {
|
|
/* as some TB could have been invalidated because
|
|
of memory exceptions while generating the code, we
|
|
must recompute the hash index here */
|
|
next_tb = 0;
|
|
tcg_ctx.tb_ctx.tb_invalidated_flag = 0;
|
|
}
|
|
if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
|
|
qemu_log("Trace %p [" TARGET_FMT_lx "] %s\n",
|
|
tb->tc_ptr, tb->pc, lookup_symbol(tb->pc));
|
|
}
|
|
/* see if we can patch the calling TB. When the TB
|
|
spans two pages, we cannot safely do a direct
|
|
jump. */
|
|
if (next_tb != 0 && tb->page_addr[1] == -1) {
|
|
tb_add_jump((TranslationBlock *)(next_tb & ~TB_EXIT_MASK),
|
|
next_tb & TB_EXIT_MASK, tb);
|
|
}
|
|
spin_unlock(&tcg_ctx.tb_ctx.tb_lock);
|
|
|
|
/* cpu_interrupt might be called while translating the
|
|
TB, but before it is linked into a potentially
|
|
infinite loop and becomes env->current_tb. Avoid
|
|
starting execution if there is a pending interrupt. */
|
|
cpu->current_tb = tb;
|
|
barrier();
|
|
if (likely(!cpu->exit_request)) {
|
|
tc_ptr = tb->tc_ptr;
|
|
/* execute the generated code */
|
|
next_tb = cpu_tb_exec(cpu, tc_ptr);
|
|
switch (next_tb & TB_EXIT_MASK) {
|
|
case TB_EXIT_REQUESTED:
|
|
/* Something asked us to stop executing
|
|
* chained TBs; just continue round the main
|
|
* loop. Whatever requested the exit will also
|
|
* have set something else (eg exit_request or
|
|
* interrupt_request) which we will handle
|
|
* next time around the loop.
|
|
*/
|
|
tb = (TranslationBlock *)(next_tb & ~TB_EXIT_MASK);
|
|
next_tb = 0;
|
|
break;
|
|
case TB_EXIT_ICOUNT_EXPIRED:
|
|
{
|
|
/* Instruction counter expired. */
|
|
int insns_left;
|
|
tb = (TranslationBlock *)(next_tb & ~TB_EXIT_MASK);
|
|
insns_left = env->icount_decr.u32;
|
|
if (env->icount_extra && insns_left >= 0) {
|
|
/* Refill decrementer and continue execution. */
|
|
env->icount_extra += insns_left;
|
|
if (env->icount_extra > 0xffff) {
|
|
insns_left = 0xffff;
|
|
} else {
|
|
insns_left = env->icount_extra;
|
|
}
|
|
env->icount_extra -= insns_left;
|
|
env->icount_decr.u16.low = insns_left;
|
|
} else {
|
|
if (insns_left > 0) {
|
|
/* Execute remaining instructions. */
|
|
cpu_exec_nocache(env, insns_left, tb);
|
|
}
|
|
env->exception_index = EXCP_INTERRUPT;
|
|
next_tb = 0;
|
|
cpu_loop_exit(env);
|
|
}
|
|
break;
|
|
}
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
cpu->current_tb = NULL;
|
|
/* reset soft MMU for next block (it can currently
|
|
only be set by a memory fault) */
|
|
} /* for(;;) */
|
|
} else {
|
|
/* Reload env after longjmp - the compiler may have smashed all
|
|
* local variables as longjmp is marked 'noreturn'. */
|
|
cpu = current_cpu;
|
|
env = cpu->env_ptr;
|
|
}
|
|
} /* for(;;) */
|
|
|
|
|
|
#if defined(TARGET_I386)
|
|
/* restore flags in standard format */
|
|
env->eflags = env->eflags | cpu_cc_compute_all(env, CC_OP)
|
|
| (env->df & DF_MASK);
|
|
#elif defined(TARGET_ARM)
|
|
/* XXX: Save/restore host fpu exception state?. */
|
|
#elif defined(TARGET_UNICORE32)
|
|
#elif defined(TARGET_SPARC)
|
|
#elif defined(TARGET_PPC)
|
|
#elif defined(TARGET_LM32)
|
|
#elif defined(TARGET_M68K)
|
|
cpu_m68k_flush_flags(env, env->cc_op);
|
|
env->cc_op = CC_OP_FLAGS;
|
|
env->sr = (env->sr & 0xffe0)
|
|
| env->cc_dest | (env->cc_x << 4);
|
|
#elif defined(TARGET_MICROBLAZE)
|
|
#elif defined(TARGET_MIPS)
|
|
#elif defined(TARGET_MOXIE)
|
|
#elif defined(TARGET_OPENRISC)
|
|
#elif defined(TARGET_SH4)
|
|
#elif defined(TARGET_ALPHA)
|
|
#elif defined(TARGET_CRIS)
|
|
#elif defined(TARGET_S390X)
|
|
#elif defined(TARGET_XTENSA)
|
|
/* XXXXX */
|
|
#else
|
|
#error unsupported target CPU
|
|
#endif
|
|
|
|
/* fail safe : never use current_cpu outside cpu_exec() */
|
|
current_cpu = NULL;
|
|
return ret;
|
|
}
|