0722d05ad8
The OCC is an on-chip microcontroller based on a ppc405 core used
for various power management tasks. It comes with a pile of additional
hardware sitting on the PIB (aka XSCOM bus). At this point we don't
emulate it (nor plan to do so). However there is one facility which
is provided by the surrounding hardware that we do need, which is the
interrupt generation facility. OPAL uses it to send itself interrupts
under some circumstances and there are other uses around the corner.
So this implement just enough to support this.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
[clg: - updated for qemu-2.9
- changed the XSCOM interface to fit new model
- QOMified the model ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
174 lines
5.1 KiB
C
174 lines
5.1 KiB
C
/*
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* QEMU PowerPC PowerNV various definitions
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*
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* Copyright (c) 2014-2016 BenH, IBM Corporation.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _PPC_PNV_H
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#define _PPC_PNV_H
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#include "hw/boards.h"
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#include "hw/sysbus.h"
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#include "hw/ppc/pnv_lpc.h"
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#include "hw/ppc/pnv_psi.h"
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#include "hw/ppc/pnv_occ.h"
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#define TYPE_PNV_CHIP "powernv-chip"
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#define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP)
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#define PNV_CHIP_CLASS(klass) \
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OBJECT_CLASS_CHECK(PnvChipClass, (klass), TYPE_PNV_CHIP)
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#define PNV_CHIP_GET_CLASS(obj) \
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OBJECT_GET_CLASS(PnvChipClass, (obj), TYPE_PNV_CHIP)
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typedef enum PnvChipType {
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PNV_CHIP_POWER8E, /* AKA Murano (default) */
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PNV_CHIP_POWER8, /* AKA Venice */
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PNV_CHIP_POWER8NVL, /* AKA Naples */
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PNV_CHIP_POWER9, /* AKA Nimbus */
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} PnvChipType;
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typedef struct PnvChip {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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uint32_t chip_id;
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uint64_t ram_start;
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uint64_t ram_size;
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uint32_t nr_cores;
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uint64_t cores_mask;
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void *cores;
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hwaddr xscom_base;
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MemoryRegion xscom_mmio;
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MemoryRegion xscom;
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AddressSpace xscom_as;
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MemoryRegion icp_mmio;
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PnvLpcController lpc;
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PnvPsi psi;
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PnvOCC occ;
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} PnvChip;
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typedef struct PnvChipClass {
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/*< private >*/
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SysBusDeviceClass parent_class;
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/*< public >*/
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const char *cpu_model;
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PnvChipType chip_type;
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uint64_t chip_cfam_id;
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uint64_t cores_mask;
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hwaddr xscom_base;
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hwaddr xscom_core_base;
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uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id);
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} PnvChipClass;
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#define TYPE_PNV_CHIP_POWER8E TYPE_PNV_CHIP "-POWER8E"
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#define PNV_CHIP_POWER8E(obj) \
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OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8E)
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#define TYPE_PNV_CHIP_POWER8 TYPE_PNV_CHIP "-POWER8"
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#define PNV_CHIP_POWER8(obj) \
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OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8)
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#define TYPE_PNV_CHIP_POWER8NVL TYPE_PNV_CHIP "-POWER8NVL"
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#define PNV_CHIP_POWER8NVL(obj) \
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OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8NVL)
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#define TYPE_PNV_CHIP_POWER9 TYPE_PNV_CHIP "-POWER9"
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#define PNV_CHIP_POWER9(obj) \
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OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER9)
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/*
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* This generates a HW chip id depending on an index, as found on a
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* two socket system with dual chip modules :
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*
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* 0x0, 0x1, 0x10, 0x11
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*
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* 4 chips should be the maximum
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*
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* TODO: use a machine property to define the chip ids
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*/
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#define PNV_CHIP_HWID(i) ((((i) & 0x3e) << 3) | ((i) & 0x1))
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/*
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* Converts back a HW chip id to an index. This is useful to calculate
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* the MMIO addresses of some controllers which depend on the chip id.
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*/
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#define PNV_CHIP_INDEX(chip) \
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(((chip)->chip_id >> 2) * 2 + ((chip)->chip_id & 0x3))
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#define TYPE_POWERNV_MACHINE MACHINE_TYPE_NAME("powernv")
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#define POWERNV_MACHINE(obj) \
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OBJECT_CHECK(PnvMachineState, (obj), TYPE_POWERNV_MACHINE)
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typedef struct PnvMachineState {
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/*< private >*/
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MachineState parent_obj;
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uint32_t initrd_base;
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long initrd_size;
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uint32_t num_chips;
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PnvChip **chips;
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ISABus *isa_bus;
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uint32_t cpld_irqstate;
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} PnvMachineState;
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#define PNV_FDT_ADDR 0x01000000
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#define PNV_TIMEBASE_FREQ 512000000ULL
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/*
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* POWER8 MMIO base addresses
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*/
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#define PNV_XSCOM_SIZE 0x800000000ull
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#define PNV_XSCOM_BASE(chip) \
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(chip->xscom_base + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE)
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/*
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* XSCOM 0x20109CA defines the ICP BAR:
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*
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* 0:29 : bits 14 to 43 of address to define 1 MB region.
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* 30 : 1 to enable ICP to receive loads/stores against its BAR region
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* 31:63 : Constant 0
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*
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* Usually defined as :
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*
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* 0xffffe00200000000 -> 0x0003ffff80000000
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* 0xffffe00600000000 -> 0x0003ffff80100000
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* 0xffffe02200000000 -> 0x0003ffff80800000
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* 0xffffe02600000000 -> 0x0003ffff80900000
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*/
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#define PNV_ICP_SIZE 0x0000000000100000ull
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#define PNV_ICP_BASE(chip) \
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(0x0003ffff80000000ull + (uint64_t) PNV_CHIP_INDEX(chip) * PNV_ICP_SIZE)
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#define PNV_PSIHB_SIZE 0x0000000000100000ull
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#define PNV_PSIHB_BASE(chip) \
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(0x0003fffe80000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * PNV_PSIHB_SIZE)
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#define PNV_PSIHB_FSP_SIZE 0x0000000100000000ull
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#define PNV_PSIHB_FSP_BASE(chip) \
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(0x0003ffe000000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * \
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PNV_PSIHB_FSP_SIZE)
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#endif /* _PPC_PNV_H */
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