Bin Meng 074ca702e6 hw/riscv: sifive_u: Correct the CLINT timebase frequency ... At present the CLINT timebase frequency is set to 10MHz on sifive_u, but on the real hardware the timebase frequency is 1Mhz. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210706102616.1922469-1-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2021-07-15 08:56:00 +10:00
..
boot.c
Kconfig	hw/riscv: Enable VIRTIO_VGA for RISC-V virt machine	2021-05-11 20:02:06 +10:00
meson.build	riscv: Add initial support for Shakti C machine	2021-05-11 20:01:38 +10:00
microchip_pfsoc.c	hw/riscv: microchip_pfsoc: Support direct kernel boot	2021-06-08 09:59:42 +10:00
numa.c
opentitan.c	hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer	2021-06-24 05:00:13 -07:00
riscv_hart.c
shakti_c.c	hw/riscv: Connect Shakti UART to Shakti platform	2021-05-11 20:02:06 +10:00
sifive_e.c
sifive_u.c	hw/riscv: sifive_u: Correct the CLINT timebase frequency	2021-07-15 08:56:00 +10:00
spike.c	hw/riscv: Use macros for BIOS image names	2021-06-08 09:59:42 +10:00
virt.c	hw/riscv: Use macros for BIOS image names	2021-06-08 09:59:42 +10:00