qemu-e2k/target
David Hildenbrand 076d4d39b6 s390x/cpumodel: wire up cpu type + id for TCG
Let's properly expose the CPU type (machine-type number) via "STORE CPU
ID" and "STORE SUBSYSTEM INFORMATION".

As TCG emulates basic mode, the CPU identification number has the format
"Annnnn", whereby A is the CPU address, and n are parts of the CPU serial
number (0 for us for now).

A specification exception will be injected if the address is not aligned
to a double word. Low address protection will not be checked as
we're missing some more general support for that.

Signed-off-by: David Hildenbrand <david@redhat.com>
Message-Id: <20170609133426.11447-3-david@redhat.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-06-13 11:09:39 -07:00
..
alpha target/alpha: Use goto_tb for fallthru between TBs 2017-06-05 09:25:42 -07:00
arm x86 and machine queue, 2017-06-05 2017-06-06 10:00:34 +01:00
cris
hppa target/hppa: Use tcg_gen_lookup_and_goto_ptr 2017-06-05 09:25:42 -07:00
i386 kvm: don't register smram_listener when smm is off 2017-06-07 18:22:02 +02:00
lm32
m68k target/m68k: implement rtd 2017-06-07 11:18:30 +02:00
microblaze
mips target/mips: optimize indirect branches 2017-06-05 09:25:42 -07:00
moxie
nios2 target/nios2: Fix 64-bit ilp32 compilation 2017-06-05 09:25:42 -07:00
openrisc target/openrisc: Support non-busy idle state using PMR SPR 2017-05-04 09:39:14 +09:00
ppc target/ppc: fix memory leak in kvmppc_is_mem_backend_page_size_ok() 2017-06-08 11:05:31 +10:00
s390x s390x/cpumodel: wire up cpu type + id for TCG 2017-06-13 11:09:39 -07:00
sh4 target/sh4: fix RTE instruction delay slot 2017-05-30 21:00:56 +02:00
sparc shutdown: Add source information to SHUTDOWN and RESET 2017-05-23 13:28:17 +02:00
tilegx migration: Remove unneeded includes of migration/vmstate.h 2017-06-01 18:49:22 +02:00
tricore
unicore32
xtensa target/xtensa: handle unknown registers in gdbstub 2017-06-06 02:40:48 -07:00