0b8fa32f55
Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190523143508.25387-4-armbru@redhat.com> [Rebased with conflicts resolved automatically, except for hw/usb/dev-hub.c hw/misc/exynos4210_rng.c hw/misc/bcm2835_rng.c hw/misc/aspeed_scu.c hw/display/virtio-vga.c hw/arm/stm32f205_soc.c; ui/cocoa.m fixed up]
379 lines
11 KiB
C
379 lines
11 KiB
C
/*
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* QEMU model of the IPI Inter Processor Interrupt block
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*
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* Copyright (c) 2014 Xilinx Inc.
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*
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* Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
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* Written by Alistair Francis <alistair.francis@xilinx.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "hw/sysbus.h"
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#include "hw/register.h"
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#include "qemu/bitops.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "hw/intc/xlnx-zynqmp-ipi.h"
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#ifndef XLNX_ZYNQMP_IPI_ERR_DEBUG
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#define XLNX_ZYNQMP_IPI_ERR_DEBUG 0
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#endif
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#define DB_PRINT_L(lvl, fmt, args...) do {\
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if (XLNX_ZYNQMP_IPI_ERR_DEBUG >= lvl) {\
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qemu_log(TYPE_XLNX_ZYNQMP_IPI ": %s:" fmt, __func__, ## args);\
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} \
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} while (0)
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#define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args)
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REG32(IPI_TRIG, 0x0)
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FIELD(IPI_TRIG, PL_3, 27, 1)
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FIELD(IPI_TRIG, PL_2, 26, 1)
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FIELD(IPI_TRIG, PL_1, 25, 1)
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FIELD(IPI_TRIG, PL_0, 24, 1)
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FIELD(IPI_TRIG, PMU_3, 19, 1)
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FIELD(IPI_TRIG, PMU_2, 18, 1)
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FIELD(IPI_TRIG, PMU_1, 17, 1)
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FIELD(IPI_TRIG, PMU_0, 16, 1)
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FIELD(IPI_TRIG, RPU_1, 9, 1)
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FIELD(IPI_TRIG, RPU_0, 8, 1)
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FIELD(IPI_TRIG, APU, 0, 1)
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REG32(IPI_OBS, 0x4)
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FIELD(IPI_OBS, PL_3, 27, 1)
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FIELD(IPI_OBS, PL_2, 26, 1)
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FIELD(IPI_OBS, PL_1, 25, 1)
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FIELD(IPI_OBS, PL_0, 24, 1)
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FIELD(IPI_OBS, PMU_3, 19, 1)
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FIELD(IPI_OBS, PMU_2, 18, 1)
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FIELD(IPI_OBS, PMU_1, 17, 1)
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FIELD(IPI_OBS, PMU_0, 16, 1)
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FIELD(IPI_OBS, RPU_1, 9, 1)
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FIELD(IPI_OBS, RPU_0, 8, 1)
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FIELD(IPI_OBS, APU, 0, 1)
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REG32(IPI_ISR, 0x10)
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FIELD(IPI_ISR, PL_3, 27, 1)
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FIELD(IPI_ISR, PL_2, 26, 1)
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FIELD(IPI_ISR, PL_1, 25, 1)
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FIELD(IPI_ISR, PL_0, 24, 1)
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FIELD(IPI_ISR, PMU_3, 19, 1)
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FIELD(IPI_ISR, PMU_2, 18, 1)
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FIELD(IPI_ISR, PMU_1, 17, 1)
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FIELD(IPI_ISR, PMU_0, 16, 1)
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FIELD(IPI_ISR, RPU_1, 9, 1)
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FIELD(IPI_ISR, RPU_0, 8, 1)
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FIELD(IPI_ISR, APU, 0, 1)
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REG32(IPI_IMR, 0x14)
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FIELD(IPI_IMR, PL_3, 27, 1)
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FIELD(IPI_IMR, PL_2, 26, 1)
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FIELD(IPI_IMR, PL_1, 25, 1)
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FIELD(IPI_IMR, PL_0, 24, 1)
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FIELD(IPI_IMR, PMU_3, 19, 1)
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FIELD(IPI_IMR, PMU_2, 18, 1)
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FIELD(IPI_IMR, PMU_1, 17, 1)
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FIELD(IPI_IMR, PMU_0, 16, 1)
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FIELD(IPI_IMR, RPU_1, 9, 1)
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FIELD(IPI_IMR, RPU_0, 8, 1)
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FIELD(IPI_IMR, APU, 0, 1)
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REG32(IPI_IER, 0x18)
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FIELD(IPI_IER, PL_3, 27, 1)
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FIELD(IPI_IER, PL_2, 26, 1)
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FIELD(IPI_IER, PL_1, 25, 1)
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FIELD(IPI_IER, PL_0, 24, 1)
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FIELD(IPI_IER, PMU_3, 19, 1)
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FIELD(IPI_IER, PMU_2, 18, 1)
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FIELD(IPI_IER, PMU_1, 17, 1)
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FIELD(IPI_IER, PMU_0, 16, 1)
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FIELD(IPI_IER, RPU_1, 9, 1)
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FIELD(IPI_IER, RPU_0, 8, 1)
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FIELD(IPI_IER, APU, 0, 1)
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REG32(IPI_IDR, 0x1c)
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FIELD(IPI_IDR, PL_3, 27, 1)
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FIELD(IPI_IDR, PL_2, 26, 1)
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FIELD(IPI_IDR, PL_1, 25, 1)
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FIELD(IPI_IDR, PL_0, 24, 1)
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FIELD(IPI_IDR, PMU_3, 19, 1)
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FIELD(IPI_IDR, PMU_2, 18, 1)
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FIELD(IPI_IDR, PMU_1, 17, 1)
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FIELD(IPI_IDR, PMU_0, 16, 1)
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FIELD(IPI_IDR, RPU_1, 9, 1)
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FIELD(IPI_IDR, RPU_0, 8, 1)
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FIELD(IPI_IDR, APU, 0, 1)
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/* APU
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* RPU_0
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* RPU_1
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* PMU_0
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* PMU_1
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* PMU_2
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* PMU_3
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* PL_0
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* PL_1
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* PL_2
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* PL_3
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*/
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int index_array[NUM_IPIS] = {0, 8, 9, 16, 17, 18, 19, 24, 25, 26, 27};
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static const char *index_array_names[NUM_IPIS] = {"APU", "RPU_0", "RPU_1",
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"PMU_0", "PMU_1", "PMU_2",
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"PMU_3", "PL_0", "PL_1",
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"PL_2", "PL_3"};
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static void xlnx_zynqmp_ipi_set_trig(XlnxZynqMPIPI *s, uint32_t val)
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{
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int i, ipi_index, ipi_mask;
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for (i = 0; i < NUM_IPIS; i++) {
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ipi_index = index_array[i];
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ipi_mask = (1 << ipi_index);
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DB_PRINT("Setting %s=%d\n", index_array_names[i],
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!!(val & ipi_mask));
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qemu_set_irq(s->irq_trig_out[i], !!(val & ipi_mask));
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}
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}
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static void xlnx_zynqmp_ipi_set_obs(XlnxZynqMPIPI *s, uint32_t val)
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{
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int i, ipi_index, ipi_mask;
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for (i = 0; i < NUM_IPIS; i++) {
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ipi_index = index_array[i];
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ipi_mask = (1 << ipi_index);
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DB_PRINT("Setting %s=%d\n", index_array_names[i],
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!!(val & ipi_mask));
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qemu_set_irq(s->irq_obs_out[i], !!(val & ipi_mask));
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}
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}
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static void xlnx_zynqmp_ipi_update_irq(XlnxZynqMPIPI *s)
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{
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bool pending = s->regs[R_IPI_ISR] & ~s->regs[R_IPI_IMR];
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DB_PRINT("irq=%d isr=%x mask=%x\n",
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pending, s->regs[R_IPI_ISR], s->regs[R_IPI_IMR]);
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qemu_set_irq(s->irq, pending);
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}
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static uint64_t xlnx_zynqmp_ipi_trig_prew(RegisterInfo *reg, uint64_t val64)
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{
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XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(reg->opaque);
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xlnx_zynqmp_ipi_set_trig(s, val64);
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return val64;
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}
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static void xlnx_zynqmp_ipi_trig_postw(RegisterInfo *reg, uint64_t val64)
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{
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XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(reg->opaque);
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/* TRIG generates a pulse on the outbound signals. We use the
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* post-write callback to bring the signal back-down.
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*/
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s->regs[R_IPI_TRIG] = 0;
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xlnx_zynqmp_ipi_set_trig(s, 0);
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}
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static uint64_t xlnx_zynqmp_ipi_isr_prew(RegisterInfo *reg, uint64_t val64)
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{
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XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(reg->opaque);
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xlnx_zynqmp_ipi_set_obs(s, val64);
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return val64;
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}
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static void xlnx_zynqmp_ipi_isr_postw(RegisterInfo *reg, uint64_t val64)
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{
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XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(reg->opaque);
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xlnx_zynqmp_ipi_update_irq(s);
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}
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static uint64_t xlnx_zynqmp_ipi_ier_prew(RegisterInfo *reg, uint64_t val64)
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{
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XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(reg->opaque);
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uint32_t val = val64;
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s->regs[R_IPI_IMR] &= ~val;
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xlnx_zynqmp_ipi_update_irq(s);
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return 0;
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}
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static uint64_t xlnx_zynqmp_ipi_idr_prew(RegisterInfo *reg, uint64_t val64)
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{
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XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(reg->opaque);
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uint32_t val = val64;
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s->regs[R_IPI_IMR] |= val;
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xlnx_zynqmp_ipi_update_irq(s);
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return 0;
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}
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static const RegisterAccessInfo xlnx_zynqmp_ipi_regs_info[] = {
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{ .name = "IPI_TRIG", .addr = A_IPI_TRIG,
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.rsvd = 0xf0f0fcfe,
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.ro = 0xf0f0fcfe,
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.pre_write = xlnx_zynqmp_ipi_trig_prew,
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.post_write = xlnx_zynqmp_ipi_trig_postw,
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},{ .name = "IPI_OBS", .addr = A_IPI_OBS,
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.rsvd = 0xf0f0fcfe,
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.ro = 0xffffffff,
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},{ .name = "IPI_ISR", .addr = A_IPI_ISR,
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.rsvd = 0xf0f0fcfe,
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.ro = 0xf0f0fcfe,
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.w1c = 0xf0f0301,
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.pre_write = xlnx_zynqmp_ipi_isr_prew,
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.post_write = xlnx_zynqmp_ipi_isr_postw,
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},{ .name = "IPI_IMR", .addr = A_IPI_IMR,
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.reset = 0xf0f0301,
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.rsvd = 0xf0f0fcfe,
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.ro = 0xffffffff,
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},{ .name = "IPI_IER", .addr = A_IPI_IER,
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.rsvd = 0xf0f0fcfe,
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.ro = 0xf0f0fcfe,
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.pre_write = xlnx_zynqmp_ipi_ier_prew,
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},{ .name = "IPI_IDR", .addr = A_IPI_IDR,
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.rsvd = 0xf0f0fcfe,
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.ro = 0xf0f0fcfe,
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.pre_write = xlnx_zynqmp_ipi_idr_prew,
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}
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};
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static void xlnx_zynqmp_ipi_reset(DeviceState *dev)
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{
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XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(dev);
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int i;
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for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
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register_reset(&s->regs_info[i]);
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}
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xlnx_zynqmp_ipi_update_irq(s);
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}
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static void xlnx_zynqmp_ipi_handler(void *opaque, int n, int level)
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{
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XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(opaque);
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uint32_t val = (!!level) << n;
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DB_PRINT("IPI input irq[%d]=%d\n", n, level);
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s->regs[R_IPI_ISR] |= val;
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xlnx_zynqmp_ipi_set_obs(s, s->regs[R_IPI_ISR]);
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xlnx_zynqmp_ipi_update_irq(s);
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}
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static void xlnx_zynqmp_obs_handler(void *opaque, int n, int level)
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{
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XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(opaque);
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DB_PRINT("OBS input irq[%d]=%d\n", n, level);
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s->regs[R_IPI_OBS] &= ~(1ULL << n);
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s->regs[R_IPI_OBS] |= (level << n);
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}
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static const MemoryRegionOps xlnx_zynqmp_ipi_ops = {
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.read = register_read_memory,
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.write = register_write_memory,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static void xlnx_zynqmp_ipi_realize(DeviceState *dev, Error **errp)
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{
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qdev_init_gpio_in_named(dev, xlnx_zynqmp_ipi_handler, "IPI_INPUTS", 32);
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qdev_init_gpio_in_named(dev, xlnx_zynqmp_obs_handler, "OBS_INPUTS", 32);
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}
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static void xlnx_zynqmp_ipi_init(Object *obj)
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{
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XlnxZynqMPIPI *s = XLNX_ZYNQMP_IPI(obj);
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DeviceState *dev = DEVICE(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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RegisterInfoArray *reg_array;
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char *irq_name;
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int i;
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memory_region_init(&s->iomem, obj, TYPE_XLNX_ZYNQMP_IPI,
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R_XLNX_ZYNQMP_IPI_MAX * 4);
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reg_array =
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register_init_block32(DEVICE(obj), xlnx_zynqmp_ipi_regs_info,
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ARRAY_SIZE(xlnx_zynqmp_ipi_regs_info),
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s->regs_info, s->regs,
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&xlnx_zynqmp_ipi_ops,
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XLNX_ZYNQMP_IPI_ERR_DEBUG,
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R_XLNX_ZYNQMP_IPI_MAX * 4);
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memory_region_add_subregion(&s->iomem,
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0x0,
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®_array->mem);
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sysbus_init_mmio(sbd, &s->iomem);
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sysbus_init_irq(sbd, &s->irq);
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for (i = 0; i < NUM_IPIS; i++) {
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qdev_init_gpio_out_named(dev, &s->irq_trig_out[i],
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index_array_names[i], 1);
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irq_name = g_strdup_printf("OBS_%s", index_array_names[i]);
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qdev_init_gpio_out_named(dev, &s->irq_obs_out[i],
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irq_name, 1);
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g_free(irq_name);
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}
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}
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static const VMStateDescription vmstate_zynqmp_pmu_ipi = {
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.name = TYPE_XLNX_ZYNQMP_IPI,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPIPI, R_XLNX_ZYNQMP_IPI_MAX),
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VMSTATE_END_OF_LIST(),
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}
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};
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static void xlnx_zynqmp_ipi_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->reset = xlnx_zynqmp_ipi_reset;
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dc->realize = xlnx_zynqmp_ipi_realize;
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dc->vmsd = &vmstate_zynqmp_pmu_ipi;
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}
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static const TypeInfo xlnx_zynqmp_ipi_info = {
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.name = TYPE_XLNX_ZYNQMP_IPI,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(XlnxZynqMPIPI),
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.class_init = xlnx_zynqmp_ipi_class_init,
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.instance_init = xlnx_zynqmp_ipi_init,
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};
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static void xlnx_zynqmp_ipi_register_types(void)
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{
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type_register_static(&xlnx_zynqmp_ipi_info);
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}
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type_init(xlnx_zynqmp_ipi_register_types)
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