0e7b176ae0
For the CPU type "any" (only used with linux-user) we were reporting the L1Ip field as 0b00, which is reserved. Change this field to 0b10 instead, indicating a VIPT icache as the comment describes. Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> Message-id: 1412966807-20844-1-git-send-email-peter.maydell@linaro.org
249 lines
8.2 KiB
C
249 lines
8.2 KiB
C
/*
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* QEMU AArch64 CPU
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*
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* Copyright (c) 2013 Linaro Ltd
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see
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* <http://www.gnu.org/licenses/gpl-2.0.html>
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*/
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#include "cpu.h"
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#include "qemu-common.h"
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#if !defined(CONFIG_USER_ONLY)
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#include "hw/loader.h"
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#endif
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#include "hw/arm/arm.h"
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#include "sysemu/sysemu.h"
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#include "sysemu/kvm.h"
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static inline void set_feature(CPUARMState *env, int feature)
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{
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env->features |= 1ULL << feature;
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}
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#ifndef CONFIG_USER_ONLY
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static uint64_t a57_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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/* Number of processors is in [25:24]; otherwise we RAZ */
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return (smp_cpus - 1) << 24;
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}
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#endif
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static const ARMCPRegInfo cortexa57_cp_reginfo[] = {
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#ifndef CONFIG_USER_ONLY
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{ .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
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.access = PL1_RW, .readfn = a57_l2ctlr_read,
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.writefn = arm_cp_write_ignore },
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{ .name = "L2CTLR",
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.cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
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.access = PL1_RW, .readfn = a57_l2ctlr_read,
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.writefn = arm_cp_write_ignore },
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#endif
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{ .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "L2ECTLR",
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.cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "CPUACTLR",
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.cp = 15, .opc1 = 0, .crm = 15,
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.access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
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{ .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "CPUECTLR",
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.cp = 15, .opc1 = 1, .crm = 15,
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.access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
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{ .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "CPUMERRSR",
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.cp = 15, .opc1 = 2, .crm = 15,
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.access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
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{ .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
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.access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
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{ .name = "L2MERRSR",
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.cp = 15, .opc1 = 3, .crm = 15,
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.access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
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REGINFO_SENTINEL
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};
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static void aarch64_a57_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V8);
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set_feature(&cpu->env, ARM_FEATURE_VFP4);
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set_feature(&cpu->env, ARM_FEATURE_NEON);
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set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
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set_feature(&cpu->env, ARM_FEATURE_AARCH64);
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set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
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set_feature(&cpu->env, ARM_FEATURE_V8_AES);
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set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
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set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
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set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
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set_feature(&cpu->env, ARM_FEATURE_CRC);
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cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
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cpu->midr = 0x411fd070;
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cpu->reset_fpsid = 0x41034070;
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cpu->mvfr0 = 0x10110222;
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cpu->mvfr1 = 0x12111111;
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cpu->mvfr2 = 0x00000043;
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cpu->ctr = 0x8444c004;
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cpu->reset_sctlr = 0x00c50838;
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cpu->id_pfr0 = 0x00000131;
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cpu->id_pfr1 = 0x00011011;
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cpu->id_dfr0 = 0x03010066;
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cpu->id_afr0 = 0x00000000;
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cpu->id_mmfr0 = 0x10101105;
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cpu->id_mmfr1 = 0x40000000;
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cpu->id_mmfr2 = 0x01260000;
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cpu->id_mmfr3 = 0x02102211;
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cpu->id_isar0 = 0x02101110;
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cpu->id_isar1 = 0x13112111;
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cpu->id_isar2 = 0x21232042;
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cpu->id_isar3 = 0x01112131;
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cpu->id_isar4 = 0x00011142;
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cpu->id_isar5 = 0x00011121;
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cpu->id_aa64pfr0 = 0x00002222;
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cpu->id_aa64dfr0 = 0x10305106;
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cpu->id_aa64isar0 = 0x00011120;
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cpu->id_aa64mmfr0 = 0x00001124;
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cpu->dbgdidr = 0x3516d000;
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cpu->clidr = 0x0a200023;
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cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
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cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
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cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
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cpu->dcz_blocksize = 4; /* 64 bytes */
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define_arm_cp_regs(cpu, cortexa57_cp_reginfo);
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}
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#ifdef CONFIG_USER_ONLY
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static void aarch64_any_initfn(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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set_feature(&cpu->env, ARM_FEATURE_V8);
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set_feature(&cpu->env, ARM_FEATURE_VFP4);
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set_feature(&cpu->env, ARM_FEATURE_NEON);
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set_feature(&cpu->env, ARM_FEATURE_AARCH64);
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set_feature(&cpu->env, ARM_FEATURE_V8_AES);
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set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
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set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
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set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
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set_feature(&cpu->env, ARM_FEATURE_CRC);
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cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
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cpu->dcz_blocksize = 7; /* 512 bytes */
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}
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#endif
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typedef struct ARMCPUInfo {
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const char *name;
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void (*initfn)(Object *obj);
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void (*class_init)(ObjectClass *oc, void *data);
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} ARMCPUInfo;
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static const ARMCPUInfo aarch64_cpus[] = {
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{ .name = "cortex-a57", .initfn = aarch64_a57_initfn },
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#ifdef CONFIG_USER_ONLY
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{ .name = "any", .initfn = aarch64_any_initfn },
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#endif
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{ .name = NULL }
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};
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static void aarch64_cpu_initfn(Object *obj)
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{
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}
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static void aarch64_cpu_finalizefn(Object *obj)
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{
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}
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static void aarch64_cpu_set_pc(CPUState *cs, vaddr value)
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{
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ARMCPU *cpu = ARM_CPU(cs);
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/* It's OK to look at env for the current mode here, because it's
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* never possible for an AArch64 TB to chain to an AArch32 TB.
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* (Otherwise we would need to use synchronize_from_tb instead.)
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*/
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if (is_a64(&cpu->env)) {
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cpu->env.pc = value;
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} else {
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cpu->env.regs[15] = value;
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}
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}
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static void aarch64_cpu_class_init(ObjectClass *oc, void *data)
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{
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CPUClass *cc = CPU_CLASS(oc);
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#if !defined(CONFIG_USER_ONLY)
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cc->do_interrupt = aarch64_cpu_do_interrupt;
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#endif
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cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
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cc->set_pc = aarch64_cpu_set_pc;
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cc->gdb_read_register = aarch64_cpu_gdb_read_register;
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cc->gdb_write_register = aarch64_cpu_gdb_write_register;
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cc->gdb_num_core_regs = 34;
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cc->gdb_core_xml_file = "aarch64-core.xml";
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}
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static void aarch64_cpu_register(const ARMCPUInfo *info)
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{
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TypeInfo type_info = {
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.parent = TYPE_AARCH64_CPU,
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.instance_size = sizeof(ARMCPU),
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.instance_init = info->initfn,
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.class_size = sizeof(ARMCPUClass),
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.class_init = info->class_init,
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};
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type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
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type_register(&type_info);
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g_free((void *)type_info.name);
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}
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static const TypeInfo aarch64_cpu_type_info = {
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.name = TYPE_AARCH64_CPU,
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.parent = TYPE_ARM_CPU,
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.instance_size = sizeof(ARMCPU),
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.instance_init = aarch64_cpu_initfn,
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.instance_finalize = aarch64_cpu_finalizefn,
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.abstract = true,
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.class_size = sizeof(AArch64CPUClass),
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.class_init = aarch64_cpu_class_init,
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};
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static void aarch64_cpu_register_types(void)
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{
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const ARMCPUInfo *info = aarch64_cpus;
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type_register_static(&aarch64_cpu_type_info);
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while (info->name) {
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aarch64_cpu_register(info);
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info++;
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}
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}
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type_init(aarch64_cpu_register_types)
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