620 lines
19 KiB
C
620 lines
19 KiB
C
/*
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* ARM Generic Interrupt Controller using KVM in-kernel support
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*
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* Copyright (c) 2012 Linaro Limited
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* Written by Peter Maydell
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* Save/Restore logic added by Christoffer Dall.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu/module.h"
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#include "migration/blocker.h"
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#include "sysemu/kvm.h"
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#include "kvm_arm.h"
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#include "gic_internal.h"
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#include "vgic_common.h"
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#include "qom/object.h"
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#define TYPE_KVM_ARM_GIC "kvm-arm-gic"
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typedef struct KVMARMGICClass KVMARMGICClass;
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/* This is reusing the GICState typedef from ARM_GIC_COMMON */
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DECLARE_OBJ_CHECKERS(GICState, KVMARMGICClass,
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KVM_ARM_GIC, TYPE_KVM_ARM_GIC)
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struct KVMARMGICClass {
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ARMGICCommonClass parent_class;
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DeviceRealize parent_realize;
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void (*parent_reset)(DeviceState *dev);
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};
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void kvm_arm_gic_set_irq(uint32_t num_irq, int irq, int level)
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{
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/* Meaning of the 'irq' parameter:
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* [0..N-1] : external interrupts
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* [N..N+31] : PPI (internal) interrupts for CPU 0
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* [N+32..N+63] : PPI (internal interrupts for CPU 1
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* ...
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* Convert this to the kernel's desired encoding, which
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* has separate fields in the irq number for type,
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* CPU number and interrupt number.
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*/
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int irqtype, cpu;
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if (irq < (num_irq - GIC_INTERNAL)) {
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/* External interrupt. The kernel numbers these like the GIC
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* hardware, with external interrupt IDs starting after the
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* internal ones.
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*/
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irqtype = KVM_ARM_IRQ_TYPE_SPI;
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cpu = 0;
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irq += GIC_INTERNAL;
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} else {
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/* Internal interrupt: decode into (cpu, interrupt id) */
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irqtype = KVM_ARM_IRQ_TYPE_PPI;
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irq -= (num_irq - GIC_INTERNAL);
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cpu = irq / GIC_INTERNAL;
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irq %= GIC_INTERNAL;
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}
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kvm_arm_set_irq(cpu, irqtype, irq, !!level);
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}
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static void kvm_arm_gicv2_set_irq(void *opaque, int irq, int level)
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{
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GICState *s = (GICState *)opaque;
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kvm_arm_gic_set_irq(s->num_irq, irq, level);
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}
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static bool kvm_arm_gic_can_save_restore(GICState *s)
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{
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return s->dev_fd >= 0;
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}
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#define KVM_VGIC_ATTR(offset, cpu) \
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((((uint64_t)(cpu) << KVM_DEV_ARM_VGIC_CPUID_SHIFT) & \
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KVM_DEV_ARM_VGIC_CPUID_MASK) | \
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(((uint64_t)(offset) << KVM_DEV_ARM_VGIC_OFFSET_SHIFT) & \
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KVM_DEV_ARM_VGIC_OFFSET_MASK))
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static void kvm_gicd_access(GICState *s, int offset, int cpu,
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uint32_t *val, bool write)
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{
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kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_DIST_REGS,
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KVM_VGIC_ATTR(offset, cpu), val, write, &error_abort);
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}
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static void kvm_gicc_access(GICState *s, int offset, int cpu,
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uint32_t *val, bool write)
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{
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kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_REGS,
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KVM_VGIC_ATTR(offset, cpu), val, write, &error_abort);
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}
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#define for_each_irq_reg(_ctr, _max_irq, _field_width) \
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for (_ctr = 0; _ctr < ((_max_irq) / (32 / (_field_width))); _ctr++)
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/*
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* Translate from the in-kernel field for an IRQ value to/from the qemu
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* representation.
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*/
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typedef void (*vgic_translate_fn)(GICState *s, int irq, int cpu,
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uint32_t *field, bool to_kernel);
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/* synthetic translate function used for clear/set registers to completely
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* clear a setting using a clear-register before setting the remaining bits
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* using a set-register */
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static void translate_clear(GICState *s, int irq, int cpu,
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uint32_t *field, bool to_kernel)
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{
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if (to_kernel) {
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*field = ~0;
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} else {
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/* does not make sense: qemu model doesn't use set/clear regs */
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abort();
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}
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}
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static void translate_group(GICState *s, int irq, int cpu,
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uint32_t *field, bool to_kernel)
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{
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int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
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if (to_kernel) {
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*field = GIC_DIST_TEST_GROUP(irq, cm);
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} else {
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if (*field & 1) {
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GIC_DIST_SET_GROUP(irq, cm);
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}
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}
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}
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static void translate_enabled(GICState *s, int irq, int cpu,
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uint32_t *field, bool to_kernel)
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{
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int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
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if (to_kernel) {
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*field = GIC_DIST_TEST_ENABLED(irq, cm);
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} else {
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if (*field & 1) {
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GIC_DIST_SET_ENABLED(irq, cm);
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}
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}
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}
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static void translate_pending(GICState *s, int irq, int cpu,
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uint32_t *field, bool to_kernel)
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{
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int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
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if (to_kernel) {
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*field = gic_test_pending(s, irq, cm);
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} else {
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if (*field & 1) {
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GIC_DIST_SET_PENDING(irq, cm);
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/* TODO: Capture is level-line is held high in the kernel */
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}
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}
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}
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static void translate_active(GICState *s, int irq, int cpu,
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uint32_t *field, bool to_kernel)
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{
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int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
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if (to_kernel) {
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*field = GIC_DIST_TEST_ACTIVE(irq, cm);
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} else {
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if (*field & 1) {
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GIC_DIST_SET_ACTIVE(irq, cm);
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}
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}
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}
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static void translate_trigger(GICState *s, int irq, int cpu,
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uint32_t *field, bool to_kernel)
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{
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if (to_kernel) {
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*field = (GIC_DIST_TEST_EDGE_TRIGGER(irq)) ? 0x2 : 0x0;
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} else {
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if (*field & 0x2) {
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GIC_DIST_SET_EDGE_TRIGGER(irq);
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}
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}
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}
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static void translate_priority(GICState *s, int irq, int cpu,
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uint32_t *field, bool to_kernel)
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{
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if (to_kernel) {
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*field = GIC_DIST_GET_PRIORITY(irq, cpu) & 0xff;
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} else {
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gic_dist_set_priority(s, cpu, irq,
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*field & 0xff, MEMTXATTRS_UNSPECIFIED);
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}
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}
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static void translate_targets(GICState *s, int irq, int cpu,
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uint32_t *field, bool to_kernel)
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{
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if (to_kernel) {
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*field = s->irq_target[irq] & 0xff;
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} else {
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s->irq_target[irq] = *field & 0xff;
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}
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}
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static void translate_sgisource(GICState *s, int irq, int cpu,
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uint32_t *field, bool to_kernel)
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{
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if (to_kernel) {
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*field = s->sgi_pending[irq][cpu] & 0xff;
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} else {
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s->sgi_pending[irq][cpu] = *field & 0xff;
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}
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}
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/* Read a register group from the kernel VGIC */
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static void kvm_dist_get(GICState *s, uint32_t offset, int width,
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int maxirq, vgic_translate_fn translate_fn)
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{
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uint32_t reg;
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int i;
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int j;
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int irq;
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int cpu;
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int regsz = 32 / width; /* irqs per kernel register */
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uint32_t field;
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for_each_irq_reg(i, maxirq, width) {
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irq = i * regsz;
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cpu = 0;
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while ((cpu < s->num_cpu && irq < GIC_INTERNAL) || cpu == 0) {
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kvm_gicd_access(s, offset, cpu, ®, false);
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for (j = 0; j < regsz; j++) {
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field = extract32(reg, j * width, width);
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translate_fn(s, irq + j, cpu, &field, false);
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}
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cpu++;
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}
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offset += 4;
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}
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}
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/* Write a register group to the kernel VGIC */
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static void kvm_dist_put(GICState *s, uint32_t offset, int width,
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int maxirq, vgic_translate_fn translate_fn)
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{
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uint32_t reg;
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int i;
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int j;
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int irq;
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int cpu;
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int regsz = 32 / width; /* irqs per kernel register */
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uint32_t field;
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for_each_irq_reg(i, maxirq, width) {
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irq = i * regsz;
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cpu = 0;
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while ((cpu < s->num_cpu && irq < GIC_INTERNAL) || cpu == 0) {
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reg = 0;
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for (j = 0; j < regsz; j++) {
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translate_fn(s, irq + j, cpu, &field, true);
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reg = deposit32(reg, j * width, width, field);
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}
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kvm_gicd_access(s, offset, cpu, ®, true);
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cpu++;
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}
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offset += 4;
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}
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}
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static void kvm_arm_gic_put(GICState *s)
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{
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uint32_t reg;
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int i;
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int cpu;
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int num_cpu;
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int num_irq;
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/* Note: We do the restore in a slightly different order than the save
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* (where the order doesn't matter and is simply ordered according to the
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* register offset values */
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/*****************************************************************
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* Distributor State
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*/
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/* s->ctlr -> GICD_CTLR */
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reg = s->ctlr;
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kvm_gicd_access(s, 0x0, 0, ®, true);
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/* Sanity checking on GICD_TYPER and s->num_irq, s->num_cpu */
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kvm_gicd_access(s, 0x4, 0, ®, false);
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num_irq = ((reg & 0x1f) + 1) * 32;
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num_cpu = ((reg & 0xe0) >> 5) + 1;
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if (num_irq < s->num_irq) {
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fprintf(stderr, "Restoring %u IRQs, but kernel supports max %d\n",
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s->num_irq, num_irq);
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abort();
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} else if (num_cpu != s->num_cpu) {
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fprintf(stderr, "Restoring %u CPU interfaces, kernel only has %d\n",
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s->num_cpu, num_cpu);
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/* Did we not create the VCPUs in the kernel yet? */
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abort();
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}
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/* TODO: Consider checking compatibility with the IIDR ? */
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/* irq_state[n].enabled -> GICD_ISENABLERn */
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kvm_dist_put(s, 0x180, 1, s->num_irq, translate_clear);
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kvm_dist_put(s, 0x100, 1, s->num_irq, translate_enabled);
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/* irq_state[n].group -> GICD_IGROUPRn */
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kvm_dist_put(s, 0x80, 1, s->num_irq, translate_group);
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/* s->irq_target[irq] -> GICD_ITARGETSRn
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* (restore targets before pending to ensure the pending state is set on
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* the appropriate CPU interfaces in the kernel) */
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kvm_dist_put(s, 0x800, 8, s->num_irq, translate_targets);
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/* irq_state[n].trigger -> GICD_ICFGRn
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* (restore configuration registers before pending IRQs so we treat
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* level/edge correctly) */
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kvm_dist_put(s, 0xc00, 2, s->num_irq, translate_trigger);
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/* irq_state[n].pending + irq_state[n].level -> GICD_ISPENDRn */
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kvm_dist_put(s, 0x280, 1, s->num_irq, translate_clear);
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kvm_dist_put(s, 0x200, 1, s->num_irq, translate_pending);
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/* irq_state[n].active -> GICD_ISACTIVERn */
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kvm_dist_put(s, 0x380, 1, s->num_irq, translate_clear);
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kvm_dist_put(s, 0x300, 1, s->num_irq, translate_active);
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/* s->priorityX[irq] -> ICD_IPRIORITYRn */
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kvm_dist_put(s, 0x400, 8, s->num_irq, translate_priority);
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/* s->sgi_pending -> ICD_CPENDSGIRn */
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kvm_dist_put(s, 0xf10, 8, GIC_NR_SGIS, translate_clear);
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kvm_dist_put(s, 0xf20, 8, GIC_NR_SGIS, translate_sgisource);
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/*****************************************************************
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* CPU Interface(s) State
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*/
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for (cpu = 0; cpu < s->num_cpu; cpu++) {
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/* s->cpu_ctlr[cpu] -> GICC_CTLR */
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reg = s->cpu_ctlr[cpu];
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kvm_gicc_access(s, 0x00, cpu, ®, true);
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/* s->priority_mask[cpu] -> GICC_PMR */
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reg = (s->priority_mask[cpu] & 0xff);
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kvm_gicc_access(s, 0x04, cpu, ®, true);
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/* s->bpr[cpu] -> GICC_BPR */
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reg = (s->bpr[cpu] & 0x7);
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kvm_gicc_access(s, 0x08, cpu, ®, true);
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/* s->abpr[cpu] -> GICC_ABPR */
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reg = (s->abpr[cpu] & 0x7);
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kvm_gicc_access(s, 0x1c, cpu, ®, true);
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/* s->apr[n][cpu] -> GICC_APRn */
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for (i = 0; i < 4; i++) {
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reg = s->apr[i][cpu];
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kvm_gicc_access(s, 0xd0 + i * 4, cpu, ®, true);
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}
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}
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}
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static void kvm_arm_gic_get(GICState *s)
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{
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uint32_t reg;
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int i;
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int cpu;
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/*****************************************************************
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* Distributor State
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*/
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/* GICD_CTLR -> s->ctlr */
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kvm_gicd_access(s, 0x0, 0, ®, false);
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s->ctlr = reg;
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/* Sanity checking on GICD_TYPER -> s->num_irq, s->num_cpu */
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kvm_gicd_access(s, 0x4, 0, ®, false);
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s->num_irq = ((reg & 0x1f) + 1) * 32;
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s->num_cpu = ((reg & 0xe0) >> 5) + 1;
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if (s->num_irq > GIC_MAXIRQ) {
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fprintf(stderr, "Too many IRQs reported from the kernel: %d\n",
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s->num_irq);
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abort();
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}
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/* GICD_IIDR -> ? */
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kvm_gicd_access(s, 0x8, 0, ®, false);
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/* Clear all the IRQ settings */
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for (i = 0; i < s->num_irq; i++) {
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memset(&s->irq_state[i], 0, sizeof(s->irq_state[0]));
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}
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/* GICD_IGROUPRn -> irq_state[n].group */
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kvm_dist_get(s, 0x80, 1, s->num_irq, translate_group);
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/* GICD_ISENABLERn -> irq_state[n].enabled */
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kvm_dist_get(s, 0x100, 1, s->num_irq, translate_enabled);
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/* GICD_ISPENDRn -> irq_state[n].pending + irq_state[n].level */
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kvm_dist_get(s, 0x200, 1, s->num_irq, translate_pending);
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/* GICD_ISACTIVERn -> irq_state[n].active */
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kvm_dist_get(s, 0x300, 1, s->num_irq, translate_active);
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/* GICD_ICFRn -> irq_state[n].trigger */
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kvm_dist_get(s, 0xc00, 2, s->num_irq, translate_trigger);
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/* GICD_IPRIORITYRn -> s->priorityX[irq] */
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kvm_dist_get(s, 0x400, 8, s->num_irq, translate_priority);
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/* GICD_ITARGETSRn -> s->irq_target[irq] */
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kvm_dist_get(s, 0x800, 8, s->num_irq, translate_targets);
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/* GICD_CPENDSGIRn -> s->sgi_pending */
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kvm_dist_get(s, 0xf10, 8, GIC_NR_SGIS, translate_sgisource);
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/*****************************************************************
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* CPU Interface(s) State
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*/
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for (cpu = 0; cpu < s->num_cpu; cpu++) {
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/* GICC_CTLR -> s->cpu_ctlr[cpu] */
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kvm_gicc_access(s, 0x00, cpu, ®, false);
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s->cpu_ctlr[cpu] = reg;
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/* GICC_PMR -> s->priority_mask[cpu] */
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kvm_gicc_access(s, 0x04, cpu, ®, false);
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s->priority_mask[cpu] = (reg & 0xff);
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/* GICC_BPR -> s->bpr[cpu] */
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kvm_gicc_access(s, 0x08, cpu, ®, false);
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s->bpr[cpu] = (reg & 0x7);
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/* GICC_ABPR -> s->abpr[cpu] */
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kvm_gicc_access(s, 0x1c, cpu, ®, false);
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s->abpr[cpu] = (reg & 0x7);
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/* GICC_APRn -> s->apr[n][cpu] */
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for (i = 0; i < 4; i++) {
|
|
kvm_gicc_access(s, 0xd0 + i * 4, cpu, ®, false);
|
|
s->apr[i][cpu] = reg;
|
|
}
|
|
}
|
|
}
|
|
|
|
static void kvm_arm_gic_reset(DeviceState *dev)
|
|
{
|
|
GICState *s = ARM_GIC_COMMON(dev);
|
|
KVMARMGICClass *kgc = KVM_ARM_GIC_GET_CLASS(s);
|
|
|
|
kgc->parent_reset(dev);
|
|
|
|
if (kvm_arm_gic_can_save_restore(s)) {
|
|
kvm_arm_gic_put(s);
|
|
}
|
|
}
|
|
|
|
static void kvm_arm_gic_realize(DeviceState *dev, Error **errp)
|
|
{
|
|
int i;
|
|
GICState *s = KVM_ARM_GIC(dev);
|
|
KVMARMGICClass *kgc = KVM_ARM_GIC_GET_CLASS(s);
|
|
Error *local_err = NULL;
|
|
int ret;
|
|
|
|
kgc->parent_realize(dev, &local_err);
|
|
if (local_err) {
|
|
error_propagate(errp, local_err);
|
|
return;
|
|
}
|
|
|
|
if (s->security_extn) {
|
|
error_setg(errp, "the in-kernel VGIC does not implement the "
|
|
"security extensions");
|
|
return;
|
|
}
|
|
|
|
if (s->virt_extn) {
|
|
error_setg(errp, "the in-kernel VGIC does not implement the "
|
|
"virtualization extensions");
|
|
return;
|
|
}
|
|
|
|
if (!kvm_arm_gic_can_save_restore(s)) {
|
|
error_setg(&s->migration_blocker, "This operating system kernel does "
|
|
"not support vGICv2 migration");
|
|
if (migrate_add_blocker(s->migration_blocker, errp) < 0) {
|
|
error_free(s->migration_blocker);
|
|
return;
|
|
}
|
|
}
|
|
|
|
gic_init_irqs_and_mmio(s, kvm_arm_gicv2_set_irq, NULL, NULL);
|
|
|
|
for (i = 0; i < s->num_irq - GIC_INTERNAL; i++) {
|
|
qemu_irq irq = qdev_get_gpio_in(dev, i);
|
|
kvm_irqchip_set_qemuirq_gsi(kvm_state, irq, i);
|
|
}
|
|
|
|
/* Try to create the device via the device control API */
|
|
s->dev_fd = -1;
|
|
ret = kvm_create_device(kvm_state, KVM_DEV_TYPE_ARM_VGIC_V2, false);
|
|
if (ret >= 0) {
|
|
s->dev_fd = ret;
|
|
|
|
/* Newstyle API is used, we may have attributes */
|
|
if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS, 0)) {
|
|
uint32_t numirqs = s->num_irq;
|
|
kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_NR_IRQS, 0,
|
|
&numirqs, true, &error_abort);
|
|
}
|
|
/* Tell the kernel to complete VGIC initialization now */
|
|
if (kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
|
|
KVM_DEV_ARM_VGIC_CTRL_INIT)) {
|
|
kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CTRL,
|
|
KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true,
|
|
&error_abort);
|
|
}
|
|
} else if (kvm_check_extension(kvm_state, KVM_CAP_DEVICE_CTRL)) {
|
|
error_setg_errno(errp, -ret, "error creating in-kernel VGIC");
|
|
error_append_hint(errp,
|
|
"Perhaps the host CPU does not support GICv2?\n");
|
|
} else if (ret != -ENODEV && ret != -ENOTSUP) {
|
|
/*
|
|
* Very ancient kernel without KVM_CAP_DEVICE_CTRL: assume that
|
|
* ENODEV or ENOTSUP mean "can't create GICv2 with KVM_CREATE_DEVICE",
|
|
* and that we will get a GICv2 via KVM_CREATE_IRQCHIP.
|
|
*/
|
|
error_setg_errno(errp, -ret, "error creating in-kernel VGIC");
|
|
return;
|
|
}
|
|
|
|
/* Distributor */
|
|
kvm_arm_register_device(&s->iomem,
|
|
(KVM_ARM_DEVICE_VGIC_V2 << KVM_ARM_DEVICE_ID_SHIFT)
|
|
| KVM_VGIC_V2_ADDR_TYPE_DIST,
|
|
KVM_DEV_ARM_VGIC_GRP_ADDR,
|
|
KVM_VGIC_V2_ADDR_TYPE_DIST,
|
|
s->dev_fd, 0);
|
|
/* CPU interface for current core. Unlike arm_gic, we don't
|
|
* provide the "interface for core #N" memory regions, because
|
|
* cores with a VGIC don't have those.
|
|
*/
|
|
kvm_arm_register_device(&s->cpuiomem[0],
|
|
(KVM_ARM_DEVICE_VGIC_V2 << KVM_ARM_DEVICE_ID_SHIFT)
|
|
| KVM_VGIC_V2_ADDR_TYPE_CPU,
|
|
KVM_DEV_ARM_VGIC_GRP_ADDR,
|
|
KVM_VGIC_V2_ADDR_TYPE_CPU,
|
|
s->dev_fd, 0);
|
|
|
|
if (kvm_has_gsi_routing()) {
|
|
/* set up irq routing */
|
|
for (i = 0; i < s->num_irq - GIC_INTERNAL; ++i) {
|
|
kvm_irqchip_add_irq_route(kvm_state, i, 0, i);
|
|
}
|
|
|
|
kvm_gsi_routing_allowed = true;
|
|
|
|
kvm_irqchip_commit_routes(kvm_state);
|
|
}
|
|
}
|
|
|
|
static void kvm_arm_gic_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
ARMGICCommonClass *agcc = ARM_GIC_COMMON_CLASS(klass);
|
|
KVMARMGICClass *kgc = KVM_ARM_GIC_CLASS(klass);
|
|
|
|
agcc->pre_save = kvm_arm_gic_get;
|
|
agcc->post_load = kvm_arm_gic_put;
|
|
device_class_set_parent_realize(dc, kvm_arm_gic_realize,
|
|
&kgc->parent_realize);
|
|
device_class_set_parent_reset(dc, kvm_arm_gic_reset, &kgc->parent_reset);
|
|
}
|
|
|
|
static const TypeInfo kvm_arm_gic_info = {
|
|
.name = TYPE_KVM_ARM_GIC,
|
|
.parent = TYPE_ARM_GIC_COMMON,
|
|
.instance_size = sizeof(GICState),
|
|
.class_init = kvm_arm_gic_class_init,
|
|
.class_size = sizeof(KVMARMGICClass),
|
|
};
|
|
|
|
static void kvm_arm_gic_register_types(void)
|
|
{
|
|
type_register_static(&kvm_arm_gic_info);
|
|
}
|
|
|
|
type_init(kvm_arm_gic_register_types)
|