359 lines
12 KiB
C
359 lines
12 KiB
C
/*
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* Allwinner H3 SDRAM Controller emulation
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*
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* Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "qemu/error-report.h"
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#include "hw/sysbus.h"
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#include "migration/vmstate.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "exec/address-spaces.h"
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#include "hw/qdev-properties.h"
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#include "qapi/error.h"
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#include "hw/misc/allwinner-h3-dramc.h"
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#include "trace.h"
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#define REG_INDEX(offset) (offset / sizeof(uint32_t))
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/* DRAMCOM register offsets */
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enum {
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REG_DRAMCOM_CR = 0x0000, /* Control Register */
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};
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/* DRAMCTL register offsets */
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enum {
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REG_DRAMCTL_PIR = 0x0000, /* PHY Initialization Register */
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REG_DRAMCTL_PGSR = 0x0010, /* PHY General Status Register */
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REG_DRAMCTL_STATR = 0x0018, /* Status Register */
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};
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/* DRAMCTL register flags */
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enum {
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REG_DRAMCTL_PGSR_INITDONE = (1 << 0),
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};
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enum {
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REG_DRAMCTL_STATR_ACTIVE = (1 << 0),
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};
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static void allwinner_h3_dramc_map_rows(AwH3DramCtlState *s, uint8_t row_bits,
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uint8_t bank_bits, uint16_t page_size)
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{
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/*
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* This function simulates row addressing behavior when bootloader
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* software attempts to detect the amount of available SDRAM. In U-Boot
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* the controller is configured with the widest row addressing available.
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* Then a pattern is written to RAM at an offset on the row boundary size.
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* If the value read back equals the value read back from the
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* start of RAM, the bootloader knows the amount of row bits.
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*
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* This function inserts a mirrored memory region when the configured row
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* bits are not matching the actual emulated memory, to simulate the
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* same behavior on hardware as expected by the bootloader.
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*/
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uint8_t row_bits_actual = 0;
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/* Calculate the actual row bits using the ram_size property */
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for (uint8_t i = 8; i < 12; i++) {
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if (1 << i == s->ram_size) {
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row_bits_actual = i + 3;
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break;
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}
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}
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if (s->ram_size == (1 << (row_bits - 3))) {
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/* When row bits is the expected value, remove the mirror */
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memory_region_set_enabled(&s->row_mirror_alias, false);
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trace_allwinner_h3_dramc_rowmirror_disable();
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} else if (row_bits_actual) {
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/* Row bits not matching ram_size, install the rows mirror */
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hwaddr row_mirror = s->ram_addr + ((1ULL << (row_bits_actual +
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bank_bits)) * page_size);
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memory_region_set_enabled(&s->row_mirror_alias, true);
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memory_region_set_address(&s->row_mirror_alias, row_mirror);
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trace_allwinner_h3_dramc_rowmirror_enable(row_mirror);
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}
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}
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static uint64_t allwinner_h3_dramcom_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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const AwH3DramCtlState *s = AW_H3_DRAMC(opaque);
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const uint32_t idx = REG_INDEX(offset);
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if (idx >= AW_H3_DRAMCOM_REGS_NUM) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
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__func__, (uint32_t)offset);
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return 0;
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}
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trace_allwinner_h3_dramcom_read(offset, s->dramcom[idx], size);
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return s->dramcom[idx];
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}
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static void allwinner_h3_dramcom_write(void *opaque, hwaddr offset,
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uint64_t val, unsigned size)
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{
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AwH3DramCtlState *s = AW_H3_DRAMC(opaque);
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const uint32_t idx = REG_INDEX(offset);
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trace_allwinner_h3_dramcom_write(offset, val, size);
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if (idx >= AW_H3_DRAMCOM_REGS_NUM) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
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__func__, (uint32_t)offset);
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return;
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}
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switch (offset) {
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case REG_DRAMCOM_CR: /* Control Register */
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allwinner_h3_dramc_map_rows(s, ((val >> 4) & 0xf) + 1,
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((val >> 2) & 0x1) + 2,
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1 << (((val >> 8) & 0xf) + 3));
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break;
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default:
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break;
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};
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s->dramcom[idx] = (uint32_t) val;
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}
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static uint64_t allwinner_h3_dramctl_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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const AwH3DramCtlState *s = AW_H3_DRAMC(opaque);
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const uint32_t idx = REG_INDEX(offset);
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if (idx >= AW_H3_DRAMCTL_REGS_NUM) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
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__func__, (uint32_t)offset);
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return 0;
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}
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trace_allwinner_h3_dramctl_read(offset, s->dramctl[idx], size);
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return s->dramctl[idx];
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}
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static void allwinner_h3_dramctl_write(void *opaque, hwaddr offset,
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uint64_t val, unsigned size)
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{
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AwH3DramCtlState *s = AW_H3_DRAMC(opaque);
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const uint32_t idx = REG_INDEX(offset);
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trace_allwinner_h3_dramctl_write(offset, val, size);
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if (idx >= AW_H3_DRAMCTL_REGS_NUM) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
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__func__, (uint32_t)offset);
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return;
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}
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switch (offset) {
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case REG_DRAMCTL_PIR: /* PHY Initialization Register */
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s->dramctl[REG_INDEX(REG_DRAMCTL_PGSR)] |= REG_DRAMCTL_PGSR_INITDONE;
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s->dramctl[REG_INDEX(REG_DRAMCTL_STATR)] |= REG_DRAMCTL_STATR_ACTIVE;
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break;
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default:
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break;
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}
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s->dramctl[idx] = (uint32_t) val;
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}
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static uint64_t allwinner_h3_dramphy_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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const AwH3DramCtlState *s = AW_H3_DRAMC(opaque);
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const uint32_t idx = REG_INDEX(offset);
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if (idx >= AW_H3_DRAMPHY_REGS_NUM) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
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__func__, (uint32_t)offset);
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return 0;
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}
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trace_allwinner_h3_dramphy_read(offset, s->dramphy[idx], size);
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return s->dramphy[idx];
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}
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static void allwinner_h3_dramphy_write(void *opaque, hwaddr offset,
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uint64_t val, unsigned size)
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{
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AwH3DramCtlState *s = AW_H3_DRAMC(opaque);
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const uint32_t idx = REG_INDEX(offset);
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trace_allwinner_h3_dramphy_write(offset, val, size);
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if (idx >= AW_H3_DRAMPHY_REGS_NUM) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
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__func__, (uint32_t)offset);
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return;
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}
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s->dramphy[idx] = (uint32_t) val;
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}
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static const MemoryRegionOps allwinner_h3_dramcom_ops = {
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.read = allwinner_h3_dramcom_read,
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.write = allwinner_h3_dramcom_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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.impl.min_access_size = 4,
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};
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static const MemoryRegionOps allwinner_h3_dramctl_ops = {
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.read = allwinner_h3_dramctl_read,
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.write = allwinner_h3_dramctl_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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.impl.min_access_size = 4,
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};
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static const MemoryRegionOps allwinner_h3_dramphy_ops = {
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.read = allwinner_h3_dramphy_read,
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.write = allwinner_h3_dramphy_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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.impl.min_access_size = 4,
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};
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static void allwinner_h3_dramc_reset(DeviceState *dev)
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{
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AwH3DramCtlState *s = AW_H3_DRAMC(dev);
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/* Set default values for registers */
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memset(&s->dramcom, 0, sizeof(s->dramcom));
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memset(&s->dramctl, 0, sizeof(s->dramctl));
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memset(&s->dramphy, 0, sizeof(s->dramphy));
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}
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static void allwinner_h3_dramc_realize(DeviceState *dev, Error **errp)
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{
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AwH3DramCtlState *s = AW_H3_DRAMC(dev);
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/* Only power of 2 RAM sizes from 256MiB up to 2048MiB are supported */
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for (uint8_t i = 8; i < 13; i++) {
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if (1 << i == s->ram_size) {
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break;
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} else if (i == 12) {
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error_report("%s: ram-size %u MiB is not supported",
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__func__, s->ram_size);
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exit(1);
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}
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}
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/* Setup row mirror mappings */
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memory_region_init_ram(&s->row_mirror, OBJECT(s),
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"allwinner-h3-dramc.row-mirror",
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4 * KiB, &error_abort);
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memory_region_add_subregion_overlap(get_system_memory(), s->ram_addr,
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&s->row_mirror, 10);
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memory_region_init_alias(&s->row_mirror_alias, OBJECT(s),
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"allwinner-h3-dramc.row-mirror-alias",
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&s->row_mirror, 0, 4 * KiB);
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memory_region_add_subregion_overlap(get_system_memory(),
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s->ram_addr + 1 * MiB,
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&s->row_mirror_alias, 10);
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memory_region_set_enabled(&s->row_mirror_alias, false);
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}
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static void allwinner_h3_dramc_init(Object *obj)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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AwH3DramCtlState *s = AW_H3_DRAMC(obj);
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/* DRAMCOM registers */
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memory_region_init_io(&s->dramcom_iomem, OBJECT(s),
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&allwinner_h3_dramcom_ops, s,
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TYPE_AW_H3_DRAMC, 4 * KiB);
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sysbus_init_mmio(sbd, &s->dramcom_iomem);
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/* DRAMCTL registers */
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memory_region_init_io(&s->dramctl_iomem, OBJECT(s),
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&allwinner_h3_dramctl_ops, s,
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TYPE_AW_H3_DRAMC, 4 * KiB);
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sysbus_init_mmio(sbd, &s->dramctl_iomem);
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/* DRAMPHY registers */
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memory_region_init_io(&s->dramphy_iomem, OBJECT(s),
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&allwinner_h3_dramphy_ops, s,
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TYPE_AW_H3_DRAMC, 4 * KiB);
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sysbus_init_mmio(sbd, &s->dramphy_iomem);
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}
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static Property allwinner_h3_dramc_properties[] = {
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DEFINE_PROP_UINT64("ram-addr", AwH3DramCtlState, ram_addr, 0x0),
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DEFINE_PROP_UINT32("ram-size", AwH3DramCtlState, ram_size, 256 * MiB),
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DEFINE_PROP_END_OF_LIST()
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};
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static const VMStateDescription allwinner_h3_dramc_vmstate = {
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.name = "allwinner-h3-dramc",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(dramcom, AwH3DramCtlState, AW_H3_DRAMCOM_REGS_NUM),
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VMSTATE_UINT32_ARRAY(dramctl, AwH3DramCtlState, AW_H3_DRAMCTL_REGS_NUM),
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VMSTATE_UINT32_ARRAY(dramphy, AwH3DramCtlState, AW_H3_DRAMPHY_REGS_NUM),
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VMSTATE_END_OF_LIST()
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}
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};
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static void allwinner_h3_dramc_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->reset = allwinner_h3_dramc_reset;
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dc->vmsd = &allwinner_h3_dramc_vmstate;
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dc->realize = allwinner_h3_dramc_realize;
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device_class_set_props(dc, allwinner_h3_dramc_properties);
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}
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static const TypeInfo allwinner_h3_dramc_info = {
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.name = TYPE_AW_H3_DRAMC,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_init = allwinner_h3_dramc_init,
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.instance_size = sizeof(AwH3DramCtlState),
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.class_init = allwinner_h3_dramc_class_init,
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};
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static void allwinner_h3_dramc_register(void)
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{
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type_register_static(&allwinner_h3_dramc_info);
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}
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type_init(allwinner_h3_dramc_register)
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