487 lines
14 KiB
C
487 lines
14 KiB
C
/*
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* ASPEED LPC Controller
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*
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* Copyright (C) 2017-2018 IBM Corp.
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*
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* This code is licensed under the GPL version 2 or later. See
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* the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/error-report.h"
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#include "hw/misc/aspeed_lpc.h"
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#include "qapi/error.h"
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#include "qapi/visitor.h"
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#include "hw/irq.h"
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#include "hw/qdev-properties.h"
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#include "migration/vmstate.h"
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#define TO_REG(offset) ((offset) >> 2)
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#define HICR0 TO_REG(0x00)
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#define HICR0_LPC3E BIT(7)
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#define HICR0_LPC2E BIT(6)
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#define HICR0_LPC1E BIT(5)
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#define HICR1 TO_REG(0x04)
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#define HICR2 TO_REG(0x08)
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#define HICR2_IBFIE3 BIT(3)
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#define HICR2_IBFIE2 BIT(2)
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#define HICR2_IBFIE1 BIT(1)
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#define HICR3 TO_REG(0x0C)
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#define HICR4 TO_REG(0x10)
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#define HICR4_KCSENBL BIT(2)
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#define IDR1 TO_REG(0x24)
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#define IDR2 TO_REG(0x28)
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#define IDR3 TO_REG(0x2C)
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#define ODR1 TO_REG(0x30)
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#define ODR2 TO_REG(0x34)
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#define ODR3 TO_REG(0x38)
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#define STR1 TO_REG(0x3C)
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#define STR_OBF BIT(0)
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#define STR_IBF BIT(1)
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#define STR_CMD_DATA BIT(3)
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#define STR2 TO_REG(0x40)
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#define STR3 TO_REG(0x44)
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#define HICR5 TO_REG(0x80)
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#define HICR6 TO_REG(0x84)
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#define HICR7 TO_REG(0x88)
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#define HICR8 TO_REG(0x8C)
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#define HICRB TO_REG(0x100)
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#define HICRB_IBFIE4 BIT(1)
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#define HICRB_LPC4E BIT(0)
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#define IDR4 TO_REG(0x114)
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#define ODR4 TO_REG(0x118)
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#define STR4 TO_REG(0x11C)
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enum aspeed_kcs_channel_id {
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kcs_channel_1 = 0,
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kcs_channel_2,
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kcs_channel_3,
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kcs_channel_4,
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};
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static const enum aspeed_lpc_subdevice aspeed_kcs_subdevice_map[] = {
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[kcs_channel_1] = aspeed_lpc_kcs_1,
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[kcs_channel_2] = aspeed_lpc_kcs_2,
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[kcs_channel_3] = aspeed_lpc_kcs_3,
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[kcs_channel_4] = aspeed_lpc_kcs_4,
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};
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struct aspeed_kcs_channel {
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enum aspeed_kcs_channel_id id;
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int idr;
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int odr;
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int str;
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};
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static const struct aspeed_kcs_channel aspeed_kcs_channel_map[] = {
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[kcs_channel_1] = {
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.id = kcs_channel_1,
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.idr = IDR1,
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.odr = ODR1,
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.str = STR1
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},
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[kcs_channel_2] = {
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.id = kcs_channel_2,
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.idr = IDR2,
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.odr = ODR2,
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.str = STR2
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},
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[kcs_channel_3] = {
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.id = kcs_channel_3,
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.idr = IDR3,
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.odr = ODR3,
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.str = STR3
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},
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[kcs_channel_4] = {
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.id = kcs_channel_4,
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.idr = IDR4,
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.odr = ODR4,
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.str = STR4
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},
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};
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struct aspeed_kcs_register_data {
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const char *name;
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int reg;
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const struct aspeed_kcs_channel *chan;
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};
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static const struct aspeed_kcs_register_data aspeed_kcs_registers[] = {
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{
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.name = "idr1",
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.reg = IDR1,
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.chan = &aspeed_kcs_channel_map[kcs_channel_1],
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},
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{
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.name = "odr1",
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.reg = ODR1,
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.chan = &aspeed_kcs_channel_map[kcs_channel_1],
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},
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{
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.name = "str1",
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.reg = STR1,
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.chan = &aspeed_kcs_channel_map[kcs_channel_1],
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},
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{
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.name = "idr2",
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.reg = IDR2,
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.chan = &aspeed_kcs_channel_map[kcs_channel_2],
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},
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{
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.name = "odr2",
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.reg = ODR2,
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.chan = &aspeed_kcs_channel_map[kcs_channel_2],
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},
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{
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.name = "str2",
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.reg = STR2,
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.chan = &aspeed_kcs_channel_map[kcs_channel_2],
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},
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{
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.name = "idr3",
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.reg = IDR3,
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.chan = &aspeed_kcs_channel_map[kcs_channel_3],
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},
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{
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.name = "odr3",
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.reg = ODR3,
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.chan = &aspeed_kcs_channel_map[kcs_channel_3],
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},
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{
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.name = "str3",
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.reg = STR3,
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.chan = &aspeed_kcs_channel_map[kcs_channel_3],
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},
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{
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.name = "idr4",
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.reg = IDR4,
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.chan = &aspeed_kcs_channel_map[kcs_channel_4],
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},
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{
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.name = "odr4",
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.reg = ODR4,
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.chan = &aspeed_kcs_channel_map[kcs_channel_4],
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},
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{
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.name = "str4",
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.reg = STR4,
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.chan = &aspeed_kcs_channel_map[kcs_channel_4],
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},
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{ },
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};
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static const struct aspeed_kcs_register_data *
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aspeed_kcs_get_register_data_by_name(const char *name)
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{
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const struct aspeed_kcs_register_data *pos = aspeed_kcs_registers;
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while (pos->name) {
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if (!strcmp(pos->name, name)) {
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return pos;
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}
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pos++;
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}
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return NULL;
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}
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static const struct aspeed_kcs_channel *
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aspeed_kcs_get_channel_by_register(int reg)
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{
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const struct aspeed_kcs_register_data *pos = aspeed_kcs_registers;
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while (pos->name) {
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if (pos->reg == reg) {
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return pos->chan;
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}
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pos++;
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}
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return NULL;
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}
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static void aspeed_kcs_get_register_property(Object *obj,
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Visitor *v,
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const char *name,
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void *opaque,
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Error **errp)
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{
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const struct aspeed_kcs_register_data *data;
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AspeedLPCState *s = ASPEED_LPC(obj);
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uint32_t val;
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data = aspeed_kcs_get_register_data_by_name(name);
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if (!data) {
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return;
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}
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if (!strncmp("odr", name, 3)) {
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s->regs[data->chan->str] &= ~STR_OBF;
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}
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val = s->regs[data->reg];
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visit_type_uint32(v, name, &val, errp);
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}
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static bool aspeed_kcs_channel_enabled(AspeedLPCState *s,
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const struct aspeed_kcs_channel *channel)
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{
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switch (channel->id) {
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case kcs_channel_1: return s->regs[HICR0] & HICR0_LPC1E;
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case kcs_channel_2: return s->regs[HICR0] & HICR0_LPC2E;
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case kcs_channel_3:
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return (s->regs[HICR0] & HICR0_LPC3E) &&
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(s->regs[HICR4] & HICR4_KCSENBL);
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case kcs_channel_4: return s->regs[HICRB] & HICRB_LPC4E;
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default: return false;
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}
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}
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static bool
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aspeed_kcs_channel_ibf_irq_enabled(AspeedLPCState *s,
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const struct aspeed_kcs_channel *channel)
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{
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if (!aspeed_kcs_channel_enabled(s, channel)) {
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return false;
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}
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switch (channel->id) {
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case kcs_channel_1: return s->regs[HICR2] & HICR2_IBFIE1;
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case kcs_channel_2: return s->regs[HICR2] & HICR2_IBFIE2;
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case kcs_channel_3: return s->regs[HICR2] & HICR2_IBFIE3;
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case kcs_channel_4: return s->regs[HICRB] & HICRB_IBFIE4;
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default: return false;
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}
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}
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static void aspeed_kcs_set_register_property(Object *obj,
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Visitor *v,
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const char *name,
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void *opaque,
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Error **errp)
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{
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const struct aspeed_kcs_register_data *data;
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AspeedLPCState *s = ASPEED_LPC(obj);
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uint32_t val;
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data = aspeed_kcs_get_register_data_by_name(name);
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if (!data) {
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return;
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}
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if (!visit_type_uint32(v, name, &val, errp)) {
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return;
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}
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if (strncmp("str", name, 3)) {
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s->regs[data->reg] = val;
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}
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if (!strncmp("idr", name, 3)) {
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s->regs[data->chan->str] |= STR_IBF;
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if (aspeed_kcs_channel_ibf_irq_enabled(s, data->chan)) {
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enum aspeed_lpc_subdevice subdev;
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subdev = aspeed_kcs_subdevice_map[data->chan->id];
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qemu_irq_raise(s->subdevice_irqs[subdev]);
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}
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}
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}
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static void aspeed_lpc_set_irq(void *opaque, int irq, int level)
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{
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AspeedLPCState *s = (AspeedLPCState *)opaque;
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if (level) {
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s->subdevice_irqs_pending |= BIT(irq);
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} else {
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s->subdevice_irqs_pending &= ~BIT(irq);
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}
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qemu_set_irq(s->irq, !!s->subdevice_irqs_pending);
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}
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static uint64_t aspeed_lpc_read(void *opaque, hwaddr offset, unsigned size)
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{
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AspeedLPCState *s = ASPEED_LPC(opaque);
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int reg = TO_REG(offset);
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if (reg >= ARRAY_SIZE(s->regs)) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
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__func__, offset);
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return 0;
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}
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switch (reg) {
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case IDR1:
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case IDR2:
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case IDR3:
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case IDR4:
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{
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const struct aspeed_kcs_channel *channel;
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channel = aspeed_kcs_get_channel_by_register(reg);
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if (s->regs[channel->str] & STR_IBF) {
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enum aspeed_lpc_subdevice subdev;
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subdev = aspeed_kcs_subdevice_map[channel->id];
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qemu_irq_lower(s->subdevice_irqs[subdev]);
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}
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s->regs[channel->str] &= ~STR_IBF;
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break;
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}
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default:
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break;
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}
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return s->regs[reg];
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}
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static void aspeed_lpc_write(void *opaque, hwaddr offset, uint64_t data,
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unsigned int size)
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{
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AspeedLPCState *s = ASPEED_LPC(opaque);
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int reg = TO_REG(offset);
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if (reg >= ARRAY_SIZE(s->regs)) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
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__func__, offset);
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return;
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}
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switch (reg) {
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case ODR1:
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case ODR2:
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case ODR3:
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case ODR4:
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s->regs[aspeed_kcs_get_channel_by_register(reg)->str] |= STR_OBF;
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break;
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default:
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break;
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}
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s->regs[reg] = data;
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}
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static const MemoryRegionOps aspeed_lpc_ops = {
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.read = aspeed_lpc_read,
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.write = aspeed_lpc_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 1,
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.max_access_size = 4,
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},
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};
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static void aspeed_lpc_reset(DeviceState *dev)
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{
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struct AspeedLPCState *s = ASPEED_LPC(dev);
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s->subdevice_irqs_pending = 0;
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memset(s->regs, 0, sizeof(s->regs));
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s->regs[HICR7] = s->hicr7;
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}
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static void aspeed_lpc_realize(DeviceState *dev, Error **errp)
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{
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AspeedLPCState *s = ASPEED_LPC(dev);
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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sysbus_init_irq(sbd, &s->irq);
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sysbus_init_irq(sbd, &s->subdevice_irqs[aspeed_lpc_kcs_1]);
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sysbus_init_irq(sbd, &s->subdevice_irqs[aspeed_lpc_kcs_2]);
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sysbus_init_irq(sbd, &s->subdevice_irqs[aspeed_lpc_kcs_3]);
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sysbus_init_irq(sbd, &s->subdevice_irqs[aspeed_lpc_kcs_4]);
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sysbus_init_irq(sbd, &s->subdevice_irqs[aspeed_lpc_ibt]);
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memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_lpc_ops, s,
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TYPE_ASPEED_LPC, 0x1000);
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sysbus_init_mmio(sbd, &s->iomem);
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qdev_init_gpio_in(dev, aspeed_lpc_set_irq, ASPEED_LPC_NR_SUBDEVS);
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}
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static void aspeed_lpc_init(Object *obj)
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{
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object_property_add(obj, "idr1", "uint32", aspeed_kcs_get_register_property,
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aspeed_kcs_set_register_property, NULL, NULL);
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object_property_add(obj, "odr1", "uint32", aspeed_kcs_get_register_property,
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aspeed_kcs_set_register_property, NULL, NULL);
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object_property_add(obj, "str1", "uint32", aspeed_kcs_get_register_property,
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aspeed_kcs_set_register_property, NULL, NULL);
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object_property_add(obj, "idr2", "uint32", aspeed_kcs_get_register_property,
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aspeed_kcs_set_register_property, NULL, NULL);
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object_property_add(obj, "odr2", "uint32", aspeed_kcs_get_register_property,
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aspeed_kcs_set_register_property, NULL, NULL);
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object_property_add(obj, "str2", "uint32", aspeed_kcs_get_register_property,
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aspeed_kcs_set_register_property, NULL, NULL);
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object_property_add(obj, "idr3", "uint32", aspeed_kcs_get_register_property,
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aspeed_kcs_set_register_property, NULL, NULL);
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object_property_add(obj, "odr3", "uint32", aspeed_kcs_get_register_property,
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aspeed_kcs_set_register_property, NULL, NULL);
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object_property_add(obj, "str3", "uint32", aspeed_kcs_get_register_property,
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aspeed_kcs_set_register_property, NULL, NULL);
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object_property_add(obj, "idr4", "uint32", aspeed_kcs_get_register_property,
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aspeed_kcs_set_register_property, NULL, NULL);
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object_property_add(obj, "odr4", "uint32", aspeed_kcs_get_register_property,
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aspeed_kcs_set_register_property, NULL, NULL);
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object_property_add(obj, "str4", "uint32", aspeed_kcs_get_register_property,
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aspeed_kcs_set_register_property, NULL, NULL);
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}
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static const VMStateDescription vmstate_aspeed_lpc = {
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.name = TYPE_ASPEED_LPC,
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.version_id = 2,
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.minimum_version_id = 2,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(regs, AspeedLPCState, ASPEED_LPC_NR_REGS),
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VMSTATE_UINT32(subdevice_irqs_pending, AspeedLPCState),
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VMSTATE_END_OF_LIST(),
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}
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};
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static Property aspeed_lpc_properties[] = {
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DEFINE_PROP_UINT32("hicr7", AspeedLPCState, hicr7, 0),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void aspeed_lpc_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = aspeed_lpc_realize;
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dc->reset = aspeed_lpc_reset;
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dc->desc = "Aspeed LPC Controller",
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dc->vmsd = &vmstate_aspeed_lpc;
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device_class_set_props(dc, aspeed_lpc_properties);
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}
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static const TypeInfo aspeed_lpc_info = {
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.name = TYPE_ASPEED_LPC,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(AspeedLPCState),
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.class_init = aspeed_lpc_class_init,
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.instance_init = aspeed_lpc_init,
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|
};
|
|
|
|
static void aspeed_lpc_register_types(void)
|
|
{
|
|
type_register_static(&aspeed_lpc_info);
|
|
}
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|
|
|
type_init(aspeed_lpc_register_types);
|