701 lines
21 KiB
C
701 lines
21 KiB
C
/*
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* QEMU NE2000 emulation
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "net/eth.h"
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#include "qemu/module.h"
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#include "exec/memory.h"
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#include "hw/irq.h"
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#include "migration/vmstate.h"
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#include "ne2000.h"
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#include "trace.h"
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/* debug NE2000 card */
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//#define DEBUG_NE2000
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#define MAX_ETH_FRAME_SIZE 1514
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#define E8390_CMD 0x00 /* The command register (for all pages) */
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/* Page 0 register offsets. */
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#define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */
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#define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */
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#define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */
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#define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */
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#define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */
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#define EN0_TSR 0x04 /* Transmit status reg RD */
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#define EN0_TPSR 0x04 /* Transmit starting page WR */
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#define EN0_NCR 0x05 /* Number of collision reg RD */
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#define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */
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#define EN0_FIFO 0x06 /* FIFO RD */
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#define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */
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#define EN0_ISR 0x07 /* Interrupt status reg RD WR */
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#define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */
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#define EN0_RSARLO 0x08 /* Remote start address reg 0 */
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#define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */
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#define EN0_RSARHI 0x09 /* Remote start address reg 1 */
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#define EN0_RCNTLO 0x0a /* Remote byte count reg WR */
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#define EN0_RTL8029ID0 0x0a /* Realtek ID byte #1 RD */
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#define EN0_RCNTHI 0x0b /* Remote byte count reg WR */
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#define EN0_RTL8029ID1 0x0b /* Realtek ID byte #2 RD */
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#define EN0_RSR 0x0c /* rx status reg RD */
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#define EN0_RXCR 0x0c /* RX configuration reg WR */
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#define EN0_TXCR 0x0d /* TX configuration reg WR */
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#define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */
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#define EN0_DCFG 0x0e /* Data configuration reg WR */
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#define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */
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#define EN0_IMR 0x0f /* Interrupt mask reg WR */
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#define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */
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#define EN1_PHYS 0x11
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#define EN1_CURPAG 0x17
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#define EN1_MULT 0x18
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#define EN2_STARTPG 0x21 /* Starting page of ring bfr RD */
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#define EN2_STOPPG 0x22 /* Ending page +1 of ring bfr RD */
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#define EN3_CONFIG0 0x33
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#define EN3_CONFIG1 0x34
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#define EN3_CONFIG2 0x35
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#define EN3_CONFIG3 0x36
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/* Register accessed at EN_CMD, the 8390 base addr. */
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#define E8390_STOP 0x01 /* Stop and reset the chip */
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#define E8390_START 0x02 /* Start the chip, clear reset */
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#define E8390_TRANS 0x04 /* Transmit a frame */
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#define E8390_RREAD 0x08 /* Remote read */
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#define E8390_RWRITE 0x10 /* Remote write */
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#define E8390_NODMA 0x20 /* Remote DMA */
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#define E8390_PAGE0 0x00 /* Select page chip registers */
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#define E8390_PAGE1 0x40 /* using the two high-order bits */
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#define E8390_PAGE2 0x80 /* Page 3 is invalid. */
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/* Bits in EN0_ISR - Interrupt status register */
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#define ENISR_RX 0x01 /* Receiver, no error */
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#define ENISR_TX 0x02 /* Transmitter, no error */
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#define ENISR_RX_ERR 0x04 /* Receiver, with error */
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#define ENISR_TX_ERR 0x08 /* Transmitter, with error */
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#define ENISR_OVER 0x10 /* Receiver overwrote the ring */
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#define ENISR_COUNTERS 0x20 /* Counters need emptying */
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#define ENISR_RDC 0x40 /* remote dma complete */
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#define ENISR_RESET 0x80 /* Reset completed */
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#define ENISR_ALL 0x3f /* Interrupts we will enable */
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/* Bits in received packet status byte and EN0_RSR*/
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#define ENRSR_RXOK 0x01 /* Received a good packet */
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#define ENRSR_CRC 0x02 /* CRC error */
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#define ENRSR_FAE 0x04 /* frame alignment error */
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#define ENRSR_FO 0x08 /* FIFO overrun */
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#define ENRSR_MPA 0x10 /* missed pkt */
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#define ENRSR_PHY 0x20 /* physical/multicast address */
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#define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */
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#define ENRSR_DEF 0x80 /* deferring */
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/* Transmitted packet status, EN0_TSR. */
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#define ENTSR_PTX 0x01 /* Packet transmitted without error */
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#define ENTSR_ND 0x02 /* The transmit wasn't deferred. */
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#define ENTSR_COL 0x04 /* The transmit collided at least once. */
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#define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */
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#define ENTSR_CRS 0x10 /* The carrier sense was lost. */
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#define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */
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#define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */
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#define ENTSR_OWC 0x80 /* There was an out-of-window collision. */
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void ne2000_reset(NE2000State *s)
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{
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int i;
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s->isr = ENISR_RESET;
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memcpy(s->mem, &s->c.macaddr, 6);
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s->mem[14] = 0x57;
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s->mem[15] = 0x57;
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/* duplicate prom data */
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for(i = 15;i >= 0; i--) {
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s->mem[2 * i] = s->mem[i];
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s->mem[2 * i + 1] = s->mem[i];
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}
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}
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static void ne2000_update_irq(NE2000State *s)
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{
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int isr;
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isr = (s->isr & s->imr) & 0x7f;
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#if defined(DEBUG_NE2000)
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printf("NE2000: Set IRQ to %d (%02x %02x)\n",
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isr ? 1 : 0, s->isr, s->imr);
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#endif
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qemu_set_irq(s->irq, (isr != 0));
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}
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static int ne2000_buffer_full(NE2000State *s)
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{
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int avail, index, boundary;
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if (s->stop <= s->start) {
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return 1;
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}
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index = s->curpag << 8;
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boundary = s->boundary << 8;
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if (index < boundary)
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avail = boundary - index;
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else
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avail = (s->stop - s->start) - (index - boundary);
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if (avail < (MAX_ETH_FRAME_SIZE + 4))
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return 1;
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return 0;
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}
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#define MIN_BUF_SIZE 60
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ssize_t ne2000_receive(NetClientState *nc, const uint8_t *buf, size_t size_)
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{
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NE2000State *s = qemu_get_nic_opaque(nc);
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size_t size = size_;
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uint8_t *p;
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unsigned int total_len, next, avail, len, index, mcast_idx;
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uint8_t buf1[60];
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static const uint8_t broadcast_macaddr[6] =
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{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
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#if defined(DEBUG_NE2000)
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printf("NE2000: received len=%zu\n", size);
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#endif
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if (s->cmd & E8390_STOP || ne2000_buffer_full(s))
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return -1;
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/* XXX: check this */
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if (s->rxcr & 0x10) {
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/* promiscuous: receive all */
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} else {
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if (!memcmp(buf, broadcast_macaddr, 6)) {
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/* broadcast address */
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if (!(s->rxcr & 0x04))
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return size;
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} else if (buf[0] & 0x01) {
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/* multicast */
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if (!(s->rxcr & 0x08))
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return size;
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mcast_idx = net_crc32(buf, ETH_ALEN) >> 26;
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if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
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return size;
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} else if (s->mem[0] == buf[0] &&
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s->mem[2] == buf[1] &&
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s->mem[4] == buf[2] &&
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s->mem[6] == buf[3] &&
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s->mem[8] == buf[4] &&
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s->mem[10] == buf[5]) {
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/* match */
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} else {
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return size;
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}
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}
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/* if too small buffer, then expand it */
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if (size < MIN_BUF_SIZE) {
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memcpy(buf1, buf, size);
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memset(buf1 + size, 0, MIN_BUF_SIZE - size);
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buf = buf1;
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size = MIN_BUF_SIZE;
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}
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index = s->curpag << 8;
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if (index >= NE2000_PMEM_END) {
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index = s->start;
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}
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/* 4 bytes for header */
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total_len = size + 4;
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/* address for next packet (4 bytes for CRC) */
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next = index + ((total_len + 4 + 255) & ~0xff);
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if (next >= s->stop)
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next -= (s->stop - s->start);
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/* prepare packet header */
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p = s->mem + index;
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s->rsr = ENRSR_RXOK; /* receive status */
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/* XXX: check this */
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if (buf[0] & 0x01)
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s->rsr |= ENRSR_PHY;
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p[0] = s->rsr;
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p[1] = next >> 8;
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p[2] = total_len;
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p[3] = total_len >> 8;
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index += 4;
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/* write packet data */
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while (size > 0) {
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if (index <= s->stop)
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avail = s->stop - index;
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else
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break;
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len = size;
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if (len > avail)
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len = avail;
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memcpy(s->mem + index, buf, len);
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buf += len;
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index += len;
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if (index == s->stop)
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index = s->start;
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size -= len;
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}
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s->curpag = next >> 8;
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/* now we can signal we have received something */
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s->isr |= ENISR_RX;
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ne2000_update_irq(s);
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return size_;
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}
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static void ne2000_ioport_write(void *opaque, uint32_t addr, uint32_t val)
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{
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NE2000State *s = opaque;
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int offset, page, index;
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addr &= 0xf;
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trace_ne2000_ioport_write(addr, val);
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if (addr == E8390_CMD) {
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/* control register */
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s->cmd = val;
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if (!(val & E8390_STOP)) { /* START bit makes no sense on RTL8029... */
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s->isr &= ~ENISR_RESET;
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/* test specific case: zero length transfer */
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if ((val & (E8390_RREAD | E8390_RWRITE)) &&
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s->rcnt == 0) {
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s->isr |= ENISR_RDC;
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ne2000_update_irq(s);
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}
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if (val & E8390_TRANS) {
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index = (s->tpsr << 8);
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/* XXX: next 2 lines are a hack to make netware 3.11 work */
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if (index >= NE2000_PMEM_END)
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index -= NE2000_PMEM_SIZE;
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/* fail safe: check range on the transmitted length */
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if (index + s->tcnt <= NE2000_PMEM_END) {
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qemu_send_packet(qemu_get_queue(s->nic), s->mem + index,
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s->tcnt);
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}
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/* signal end of transfer */
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s->tsr = ENTSR_PTX;
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s->isr |= ENISR_TX;
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s->cmd &= ~E8390_TRANS;
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ne2000_update_irq(s);
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}
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}
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} else {
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page = s->cmd >> 6;
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offset = addr | (page << 4);
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switch(offset) {
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case EN0_STARTPG:
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if (val << 8 <= NE2000_PMEM_END) {
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s->start = val << 8;
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}
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break;
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case EN0_STOPPG:
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if (val << 8 <= NE2000_PMEM_END) {
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s->stop = val << 8;
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}
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break;
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case EN0_BOUNDARY:
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if (val << 8 < NE2000_PMEM_END) {
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s->boundary = val;
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}
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break;
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case EN0_IMR:
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s->imr = val;
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ne2000_update_irq(s);
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break;
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case EN0_TPSR:
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s->tpsr = val;
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break;
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case EN0_TCNTLO:
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s->tcnt = (s->tcnt & 0xff00) | val;
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break;
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case EN0_TCNTHI:
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s->tcnt = (s->tcnt & 0x00ff) | (val << 8);
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break;
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case EN0_RSARLO:
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s->rsar = (s->rsar & 0xff00) | val;
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break;
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case EN0_RSARHI:
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s->rsar = (s->rsar & 0x00ff) | (val << 8);
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break;
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case EN0_RCNTLO:
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s->rcnt = (s->rcnt & 0xff00) | val;
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break;
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case EN0_RCNTHI:
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s->rcnt = (s->rcnt & 0x00ff) | (val << 8);
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break;
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case EN0_RXCR:
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s->rxcr = val;
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break;
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case EN0_DCFG:
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s->dcfg = val;
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break;
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case EN0_ISR:
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s->isr &= ~(val & 0x7f);
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ne2000_update_irq(s);
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break;
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case EN1_PHYS ... EN1_PHYS + 5:
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s->phys[offset - EN1_PHYS] = val;
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break;
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case EN1_CURPAG:
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if (val << 8 < NE2000_PMEM_END) {
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s->curpag = val;
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}
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break;
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case EN1_MULT ... EN1_MULT + 7:
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s->mult[offset - EN1_MULT] = val;
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break;
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}
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}
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}
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static uint32_t ne2000_ioport_read(void *opaque, uint32_t addr)
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{
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NE2000State *s = opaque;
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int offset, page, ret;
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addr &= 0xf;
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if (addr == E8390_CMD) {
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ret = s->cmd;
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} else {
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page = s->cmd >> 6;
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offset = addr | (page << 4);
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switch(offset) {
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case EN0_TSR:
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ret = s->tsr;
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break;
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case EN0_BOUNDARY:
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ret = s->boundary;
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break;
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case EN0_ISR:
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ret = s->isr;
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break;
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case EN0_RSARLO:
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ret = s->rsar & 0x00ff;
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break;
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case EN0_RSARHI:
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ret = s->rsar >> 8;
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break;
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case EN1_PHYS ... EN1_PHYS + 5:
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ret = s->phys[offset - EN1_PHYS];
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break;
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case EN1_CURPAG:
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ret = s->curpag;
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break;
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case EN1_MULT ... EN1_MULT + 7:
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ret = s->mult[offset - EN1_MULT];
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break;
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case EN0_RSR:
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ret = s->rsr;
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break;
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case EN2_STARTPG:
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ret = s->start >> 8;
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break;
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case EN2_STOPPG:
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ret = s->stop >> 8;
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break;
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case EN0_RTL8029ID0:
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ret = 0x50;
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break;
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case EN0_RTL8029ID1:
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ret = 0x43;
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break;
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case EN3_CONFIG0:
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ret = 0; /* 10baseT media */
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break;
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case EN3_CONFIG2:
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ret = 0x40; /* 10baseT active */
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break;
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case EN3_CONFIG3:
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ret = 0x40; /* Full duplex */
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break;
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default:
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ret = 0x00;
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break;
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}
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}
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trace_ne2000_ioport_read(addr, ret);
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return ret;
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}
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static inline void ne2000_mem_writeb(NE2000State *s, uint32_t addr,
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uint32_t val)
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{
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if (addr < 32 ||
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(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
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s->mem[addr] = val;
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}
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}
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static inline void ne2000_mem_writew(NE2000State *s, uint32_t addr,
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uint32_t val)
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{
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addr &= ~1; /* XXX: check exact behaviour if not even */
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if (addr < 32 ||
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(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
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*(uint16_t *)(s->mem + addr) = cpu_to_le16(val);
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}
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}
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static inline void ne2000_mem_writel(NE2000State *s, uint32_t addr,
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uint32_t val)
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{
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addr &= ~1; /* XXX: check exact behaviour if not even */
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if (addr < 32
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|| (addr >= NE2000_PMEM_START
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&& addr + sizeof(uint32_t) <= NE2000_MEM_SIZE)) {
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stl_le_p(s->mem + addr, val);
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}
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}
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static inline uint32_t ne2000_mem_readb(NE2000State *s, uint32_t addr)
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{
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if (addr < 32 ||
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(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
|
|
return s->mem[addr];
|
|
} else {
|
|
return 0xff;
|
|
}
|
|
}
|
|
|
|
static inline uint32_t ne2000_mem_readw(NE2000State *s, uint32_t addr)
|
|
{
|
|
addr &= ~1; /* XXX: check exact behaviour if not even */
|
|
if (addr < 32 ||
|
|
(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
|
|
return le16_to_cpu(*(uint16_t *)(s->mem + addr));
|
|
} else {
|
|
return 0xffff;
|
|
}
|
|
}
|
|
|
|
static inline uint32_t ne2000_mem_readl(NE2000State *s, uint32_t addr)
|
|
{
|
|
addr &= ~1; /* XXX: check exact behaviour if not even */
|
|
if (addr < 32
|
|
|| (addr >= NE2000_PMEM_START
|
|
&& addr + sizeof(uint32_t) <= NE2000_MEM_SIZE)) {
|
|
return ldl_le_p(s->mem + addr);
|
|
} else {
|
|
return 0xffffffff;
|
|
}
|
|
}
|
|
|
|
static inline void ne2000_dma_update(NE2000State *s, int len)
|
|
{
|
|
s->rsar += len;
|
|
/* wrap */
|
|
/* XXX: check what to do if rsar > stop */
|
|
if (s->rsar == s->stop)
|
|
s->rsar = s->start;
|
|
|
|
if (s->rcnt <= len) {
|
|
s->rcnt = 0;
|
|
/* signal end of transfer */
|
|
s->isr |= ENISR_RDC;
|
|
ne2000_update_irq(s);
|
|
} else {
|
|
s->rcnt -= len;
|
|
}
|
|
}
|
|
|
|
static void ne2000_asic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
|
|
{
|
|
NE2000State *s = opaque;
|
|
|
|
#ifdef DEBUG_NE2000
|
|
printf("NE2000: asic write val=0x%04x\n", val);
|
|
#endif
|
|
if (s->rcnt == 0)
|
|
return;
|
|
if (s->dcfg & 0x01) {
|
|
/* 16 bit access */
|
|
ne2000_mem_writew(s, s->rsar, val);
|
|
ne2000_dma_update(s, 2);
|
|
} else {
|
|
/* 8 bit access */
|
|
ne2000_mem_writeb(s, s->rsar, val);
|
|
ne2000_dma_update(s, 1);
|
|
}
|
|
}
|
|
|
|
static uint32_t ne2000_asic_ioport_read(void *opaque, uint32_t addr)
|
|
{
|
|
NE2000State *s = opaque;
|
|
int ret;
|
|
|
|
if (s->dcfg & 0x01) {
|
|
/* 16 bit access */
|
|
ret = ne2000_mem_readw(s, s->rsar);
|
|
ne2000_dma_update(s, 2);
|
|
} else {
|
|
/* 8 bit access */
|
|
ret = ne2000_mem_readb(s, s->rsar);
|
|
ne2000_dma_update(s, 1);
|
|
}
|
|
#ifdef DEBUG_NE2000
|
|
printf("NE2000: asic read val=0x%04x\n", ret);
|
|
#endif
|
|
return ret;
|
|
}
|
|
|
|
static void ne2000_asic_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
|
|
{
|
|
NE2000State *s = opaque;
|
|
|
|
#ifdef DEBUG_NE2000
|
|
printf("NE2000: asic writel val=0x%04x\n", val);
|
|
#endif
|
|
if (s->rcnt == 0)
|
|
return;
|
|
/* 32 bit access */
|
|
ne2000_mem_writel(s, s->rsar, val);
|
|
ne2000_dma_update(s, 4);
|
|
}
|
|
|
|
static uint32_t ne2000_asic_ioport_readl(void *opaque, uint32_t addr)
|
|
{
|
|
NE2000State *s = opaque;
|
|
int ret;
|
|
|
|
/* 32 bit access */
|
|
ret = ne2000_mem_readl(s, s->rsar);
|
|
ne2000_dma_update(s, 4);
|
|
#ifdef DEBUG_NE2000
|
|
printf("NE2000: asic readl val=0x%04x\n", ret);
|
|
#endif
|
|
return ret;
|
|
}
|
|
|
|
static void ne2000_reset_ioport_write(void *opaque, uint32_t addr, uint32_t val)
|
|
{
|
|
/* nothing to do (end of reset pulse) */
|
|
}
|
|
|
|
static uint32_t ne2000_reset_ioport_read(void *opaque, uint32_t addr)
|
|
{
|
|
NE2000State *s = opaque;
|
|
ne2000_reset(s);
|
|
return 0;
|
|
}
|
|
|
|
static int ne2000_post_load(void* opaque, int version_id)
|
|
{
|
|
NE2000State* s = opaque;
|
|
|
|
if (version_id < 2) {
|
|
s->rxcr = 0x0c;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
const VMStateDescription vmstate_ne2000 = {
|
|
.name = "ne2000",
|
|
.version_id = 2,
|
|
.minimum_version_id = 0,
|
|
.post_load = ne2000_post_load,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_UINT8_V(rxcr, NE2000State, 2),
|
|
VMSTATE_UINT8(cmd, NE2000State),
|
|
VMSTATE_UINT32(start, NE2000State),
|
|
VMSTATE_UINT32(stop, NE2000State),
|
|
VMSTATE_UINT8(boundary, NE2000State),
|
|
VMSTATE_UINT8(tsr, NE2000State),
|
|
VMSTATE_UINT8(tpsr, NE2000State),
|
|
VMSTATE_UINT16(tcnt, NE2000State),
|
|
VMSTATE_UINT16(rcnt, NE2000State),
|
|
VMSTATE_UINT32(rsar, NE2000State),
|
|
VMSTATE_UINT8(rsr, NE2000State),
|
|
VMSTATE_UINT8(isr, NE2000State),
|
|
VMSTATE_UINT8(dcfg, NE2000State),
|
|
VMSTATE_UINT8(imr, NE2000State),
|
|
VMSTATE_BUFFER(phys, NE2000State),
|
|
VMSTATE_UINT8(curpag, NE2000State),
|
|
VMSTATE_BUFFER(mult, NE2000State),
|
|
VMSTATE_UNUSED(4), /* was irq */
|
|
VMSTATE_BUFFER(mem, NE2000State),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static uint64_t ne2000_read(void *opaque, hwaddr addr,
|
|
unsigned size)
|
|
{
|
|
NE2000State *s = opaque;
|
|
uint64_t val;
|
|
|
|
if (addr < 0x10 && size == 1) {
|
|
val = ne2000_ioport_read(s, addr);
|
|
} else if (addr == 0x10) {
|
|
if (size <= 2) {
|
|
val = ne2000_asic_ioport_read(s, addr);
|
|
} else {
|
|
val = ne2000_asic_ioport_readl(s, addr);
|
|
}
|
|
} else if (addr == 0x1f && size == 1) {
|
|
val = ne2000_reset_ioport_read(s, addr);
|
|
} else {
|
|
val = ((uint64_t)1 << (size * 8)) - 1;
|
|
}
|
|
trace_ne2000_read(addr, val);
|
|
|
|
return val;
|
|
}
|
|
|
|
static void ne2000_write(void *opaque, hwaddr addr,
|
|
uint64_t data, unsigned size)
|
|
{
|
|
NE2000State *s = opaque;
|
|
|
|
trace_ne2000_write(addr, data);
|
|
if (addr < 0x10 && size == 1) {
|
|
ne2000_ioport_write(s, addr, data);
|
|
} else if (addr == 0x10) {
|
|
if (size <= 2) {
|
|
ne2000_asic_ioport_write(s, addr, data);
|
|
} else {
|
|
ne2000_asic_ioport_writel(s, addr, data);
|
|
}
|
|
} else if (addr == 0x1f && size == 1) {
|
|
ne2000_reset_ioport_write(s, addr, data);
|
|
}
|
|
}
|
|
|
|
static const MemoryRegionOps ne2000_ops = {
|
|
.read = ne2000_read,
|
|
.write = ne2000_write,
|
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
|
};
|
|
|
|
/***********************************************************/
|
|
/* PCI NE2000 definitions */
|
|
|
|
void ne2000_setup_io(NE2000State *s, DeviceState *dev, unsigned size)
|
|
{
|
|
memory_region_init_io(&s->io, OBJECT(dev), &ne2000_ops, s, "ne2000", size);
|
|
}
|