182 lines
4.4 KiB
C
182 lines
4.4 KiB
C
/*
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* ASPEED Real Time Clock
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* Joel Stanley <joel@jms.id.au>
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*
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* Copyright 2019 IBM Corp
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "qemu-common.h"
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#include "hw/rtc/aspeed_rtc.h"
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#include "migration/vmstate.h"
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#include "qemu/log.h"
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#include "qemu/timer.h"
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#include "trace.h"
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#define COUNTER1 (0x00 / 4)
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#define COUNTER2 (0x04 / 4)
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#define ALARM (0x08 / 4)
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#define CONTROL (0x10 / 4)
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#define ALARM_STATUS (0x14 / 4)
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#define RTC_UNLOCKED BIT(1)
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#define RTC_ENABLED BIT(0)
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static void aspeed_rtc_calc_offset(AspeedRtcState *rtc)
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{
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struct tm tm;
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uint32_t year, cent;
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uint32_t reg1 = rtc->reg[COUNTER1];
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uint32_t reg2 = rtc->reg[COUNTER2];
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tm.tm_mday = (reg1 >> 24) & 0x1f;
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tm.tm_hour = (reg1 >> 16) & 0x1f;
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tm.tm_min = (reg1 >> 8) & 0x3f;
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tm.tm_sec = (reg1 >> 0) & 0x3f;
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cent = (reg2 >> 16) & 0x1f;
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year = (reg2 >> 8) & 0x7f;
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tm.tm_mon = ((reg2 >> 0) & 0x0f) - 1;
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tm.tm_year = year + (cent * 100) - 1900;
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rtc->offset = qemu_timedate_diff(&tm);
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}
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static uint32_t aspeed_rtc_get_counter(AspeedRtcState *rtc, int r)
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{
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uint32_t year, cent;
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struct tm now;
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qemu_get_timedate(&now, rtc->offset);
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switch (r) {
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case COUNTER1:
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return (now.tm_mday << 24) | (now.tm_hour << 16) |
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(now.tm_min << 8) | now.tm_sec;
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case COUNTER2:
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cent = (now.tm_year + 1900) / 100;
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year = now.tm_year % 100;
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return ((cent & 0x1f) << 16) | ((year & 0x7f) << 8) |
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((now.tm_mon + 1) & 0xf);
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default:
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g_assert_not_reached();
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}
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}
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static uint64_t aspeed_rtc_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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AspeedRtcState *rtc = opaque;
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uint64_t val;
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uint32_t r = addr >> 2;
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switch (r) {
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case COUNTER1:
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case COUNTER2:
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if (rtc->reg[CONTROL] & RTC_ENABLED) {
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rtc->reg[r] = aspeed_rtc_get_counter(rtc, r);
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}
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/* fall through */
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case CONTROL:
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val = rtc->reg[r];
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break;
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case ALARM:
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case ALARM_STATUS:
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default:
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qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx "\n", __func__, addr);
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return 0;
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}
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trace_aspeed_rtc_read(addr, val);
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return val;
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}
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static void aspeed_rtc_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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AspeedRtcState *rtc = opaque;
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uint32_t r = addr >> 2;
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switch (r) {
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case COUNTER1:
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case COUNTER2:
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if (!(rtc->reg[CONTROL] & RTC_UNLOCKED)) {
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break;
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}
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/* fall through */
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case CONTROL:
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rtc->reg[r] = val;
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aspeed_rtc_calc_offset(rtc);
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break;
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case ALARM:
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case ALARM_STATUS:
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default:
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qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx "\n", __func__, addr);
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break;
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}
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trace_aspeed_rtc_write(addr, val);
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}
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static void aspeed_rtc_reset(DeviceState *d)
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{
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AspeedRtcState *rtc = ASPEED_RTC(d);
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rtc->offset = 0;
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memset(rtc->reg, 0, sizeof(rtc->reg));
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}
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static const MemoryRegionOps aspeed_rtc_ops = {
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.read = aspeed_rtc_read,
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.write = aspeed_rtc_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static const VMStateDescription vmstate_aspeed_rtc = {
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.name = TYPE_ASPEED_RTC,
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.version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(reg, AspeedRtcState, 0x18),
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VMSTATE_INT32(offset, AspeedRtcState),
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VMSTATE_INT32(offset, AspeedRtcState),
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VMSTATE_END_OF_LIST()
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}
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};
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static void aspeed_rtc_realize(DeviceState *dev, Error **errp)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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AspeedRtcState *s = ASPEED_RTC(dev);
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sysbus_init_irq(sbd, &s->irq);
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memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_rtc_ops, s,
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"aspeed-rtc", 0x18ULL);
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sysbus_init_mmio(sbd, &s->iomem);
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}
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static void aspeed_rtc_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = aspeed_rtc_realize;
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dc->vmsd = &vmstate_aspeed_rtc;
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dc->reset = aspeed_rtc_reset;
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}
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static const TypeInfo aspeed_rtc_info = {
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.name = TYPE_ASPEED_RTC,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(AspeedRtcState),
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.class_init = aspeed_rtc_class_init,
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};
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static void aspeed_rtc_register_types(void)
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{
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type_register_static(&aspeed_rtc_info);
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}
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type_init(aspeed_rtc_register_types)
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