216 lines
6.5 KiB
C
216 lines
6.5 KiB
C
/*
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* QEMU PCI VGA Emulator.
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*
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* see docs/specs/standard-vga.txt for virtual hardware specs.
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h"
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#include "console.h"
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#include "pci.h"
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#include "vga_int.h"
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#include "pixel_ops.h"
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#include "qemu-timer.h"
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#include "loader.h"
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#define PCI_VGA_IOPORT_OFFSET 0x400
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#define PCI_VGA_IOPORT_SIZE (0x3e0 - 0x3c0)
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#define PCI_VGA_BOCHS_OFFSET 0x500
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#define PCI_VGA_BOCHS_SIZE (0x0b * 2)
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#define PCI_VGA_MMIO_SIZE 0x1000
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enum vga_pci_flags {
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PCI_VGA_FLAG_ENABLE_MMIO = 1,
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};
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typedef struct PCIVGAState {
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PCIDevice dev;
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VGACommonState vga;
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uint32_t flags;
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MemoryRegion mmio;
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MemoryRegion ioport;
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MemoryRegion bochs;
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} PCIVGAState;
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static const VMStateDescription vmstate_vga_pci = {
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.name = "vga",
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.version_id = 2,
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.minimum_version_id = 2,
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.minimum_version_id_old = 2,
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.fields = (VMStateField []) {
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VMSTATE_PCI_DEVICE(dev, PCIVGAState),
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VMSTATE_STRUCT(vga, PCIVGAState, 0, vmstate_vga_common, VGACommonState),
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VMSTATE_END_OF_LIST()
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}
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};
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static uint64_t pci_vga_ioport_read(void *ptr, hwaddr addr,
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unsigned size)
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{
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PCIVGAState *d = ptr;
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uint64_t ret = 0;
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switch (size) {
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case 1:
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ret = vga_ioport_read(&d->vga, addr);
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break;
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case 2:
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ret = vga_ioport_read(&d->vga, addr);
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ret |= vga_ioport_read(&d->vga, addr+1) << 8;
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break;
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}
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return ret;
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}
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static void pci_vga_ioport_write(void *ptr, hwaddr addr,
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uint64_t val, unsigned size)
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{
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PCIVGAState *d = ptr;
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switch (size) {
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case 1:
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vga_ioport_write(&d->vga, addr + 0x3c0, val);
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break;
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case 2:
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/*
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* Update bytes in little endian order. Allows to update
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* indexed registers with a single word write because the
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* index byte is updated first.
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*/
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vga_ioport_write(&d->vga, addr + 0x3c0, val & 0xff);
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vga_ioport_write(&d->vga, addr + 0x3c1, (val >> 8) & 0xff);
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break;
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}
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}
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static const MemoryRegionOps pci_vga_ioport_ops = {
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.read = pci_vga_ioport_read,
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.write = pci_vga_ioport_write,
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.valid.min_access_size = 1,
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.valid.max_access_size = 4,
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.impl.min_access_size = 1,
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.impl.max_access_size = 2,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static uint64_t pci_vga_bochs_read(void *ptr, hwaddr addr,
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unsigned size)
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{
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PCIVGAState *d = ptr;
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int index = addr >> 1;
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vbe_ioport_write_index(&d->vga, 0, index);
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return vbe_ioport_read_data(&d->vga, 0);
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}
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static void pci_vga_bochs_write(void *ptr, hwaddr addr,
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uint64_t val, unsigned size)
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{
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PCIVGAState *d = ptr;
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int index = addr >> 1;
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vbe_ioport_write_index(&d->vga, 0, index);
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vbe_ioport_write_data(&d->vga, 0, val);
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}
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static const MemoryRegionOps pci_vga_bochs_ops = {
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.read = pci_vga_bochs_read,
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.write = pci_vga_bochs_write,
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.valid.min_access_size = 1,
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.valid.max_access_size = 4,
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.impl.min_access_size = 2,
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.impl.max_access_size = 2,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static int pci_std_vga_initfn(PCIDevice *dev)
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{
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PCIVGAState *d = DO_UPCAST(PCIVGAState, dev, dev);
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VGACommonState *s = &d->vga;
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/* vga + console init */
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vga_common_init(s);
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vga_init(s, pci_address_space(dev), pci_address_space_io(dev), true);
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s->ds = graphic_console_init(s->update, s->invalidate,
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s->screen_dump, s->text_update, s);
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/* XXX: VGA_RAM_SIZE must be a power of two */
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pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram);
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/* mmio bar for vga register access */
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if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_MMIO)) {
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memory_region_init(&d->mmio, "vga.mmio", 4096);
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memory_region_init_io(&d->ioport, &pci_vga_ioport_ops, d,
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"vga ioports remapped", PCI_VGA_IOPORT_SIZE);
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memory_region_init_io(&d->bochs, &pci_vga_bochs_ops, d,
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"bochs dispi interface", PCI_VGA_BOCHS_SIZE);
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memory_region_add_subregion(&d->mmio, PCI_VGA_IOPORT_OFFSET,
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&d->ioport);
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memory_region_add_subregion(&d->mmio, PCI_VGA_BOCHS_OFFSET,
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&d->bochs);
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pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
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}
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if (!dev->rom_bar) {
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/* compatibility with pc-0.13 and older */
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vga_init_vbe(s, pci_address_space(dev));
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}
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return 0;
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}
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static Property vga_pci_properties[] = {
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DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16),
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DEFINE_PROP_BIT("mmio", PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_MMIO, true),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void vga_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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k->no_hotplug = 1;
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k->init = pci_std_vga_initfn;
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k->romfile = "vgabios-stdvga.bin";
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k->vendor_id = PCI_VENDOR_ID_QEMU;
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k->device_id = PCI_DEVICE_ID_QEMU_VGA;
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k->class_id = PCI_CLASS_DISPLAY_VGA;
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dc->vmsd = &vmstate_vga_pci;
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dc->props = vga_pci_properties;
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}
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static TypeInfo vga_info = {
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.name = "VGA",
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(PCIVGAState),
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.class_init = vga_class_init,
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};
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static void vga_register_types(void)
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{
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type_register_static(&vga_info);
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}
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type_init(vga_register_types)
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