01e0451a08
This reverts commit8ef9ea85a2, reversing changes made to444dc48298. From Avi: Please revert the entire pull (git revert8ef9ea85a2) while I work this out - it isn't trivial. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
61 lines
2.4 KiB
C
61 lines
2.4 KiB
C
/*
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* QEMU Common PCI Host bridge configuration data space access routines.
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*
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* Copyright (c) 2006 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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/* Worker routines for a PCI host controller that uses an {address,data}
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register pair to access PCI configuration space. */
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#ifndef PCI_HOST_H
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#define PCI_HOST_H
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#include "sysbus.h"
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#include "rwhandler.h"
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struct PCIHostState {
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SysBusDevice busdev;
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ReadWriteHandler conf_handler;
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ReadWriteHandler data_handler;
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MemoryRegion *address_space;
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uint32_t config_reg;
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PCIBus *bus;
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};
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/* common internal helpers for PCI/PCIe hosts, cut off overflows */
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void pci_host_config_write_common(PCIDevice *pci_dev, uint32_t addr,
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uint32_t limit, uint32_t val, uint32_t len);
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uint32_t pci_host_config_read_common(PCIDevice *pci_dev, uint32_t addr,
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uint32_t limit, uint32_t len);
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void pci_data_write(PCIBus *s, uint32_t addr, uint32_t val, int len);
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uint32_t pci_data_read(PCIBus *s, uint32_t addr, int len);
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/* for mmio */
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int pci_host_conf_register_mmio(PCIHostState *s, int endian);
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int pci_host_data_register_mmio(PCIHostState *s, int endian);
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/* for ioio */
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void pci_host_conf_register_ioport(pio_addr_t ioport, PCIHostState *s);
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void pci_host_data_register_ioport(pio_addr_t ioport, PCIHostState *s);
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#endif /* PCI_HOST_H */
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