qemu-e2k/target
Richard Henderson 0a54d68e21 target/arm: Hoist computation of TBFLAG_A32.VFPEN
There are 3 conditions that each enable this flag.  M-profile always
enables; A-profile with EL1 as AA64 always enables.  Both of these
conditions can easily be cached.  The final condition relies on the
FPEXC register which we are not prepared to cache.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20191023150057.25731-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-10-24 17:16:28 +01:00
..
alpha target/alpha: Tidy helper_fp_exc_raise_s 2019-09-26 19:00:53 +01:00
arm target/arm: Hoist computation of TBFLAG_A32.VFPEN 2019-10-24 17:16:28 +01:00
cris
hppa target/hppa: prevent trashing of temporary in do_depw_sar() 2019-09-14 15:39:24 -04:00
i386 target/i386: Introduce Denverton CPU model 2019-10-23 23:37:42 -03:00
lm32
m68k target/m68k/fpu_helper.c: rename the access arguments 2019-09-19 12:12:19 +02:00
microblaze tcg: TCGMemOp is now accelerator independent MemOp 2019-09-03 08:30:38 -07:00
mips target/mips: msa: Move helpers for <AND|NOR|OR|XOR>.V 2019-10-01 16:58:45 +02:00
moxie
nios2
openrisc target/openrisc: Update cpu "any" to v1.3 2019-09-04 13:01:56 -07:00
ppc target/ppc: Fix for optimized vsl/vsr instructions 2019-10-24 09:36:55 +11:00
riscv gdbstub: riscv: fix the fflags registers 2019-09-17 08:42:50 -07:00
s390x s390x/kvm: Set default cpu model for all machine classes 2019-10-21 18:03:08 +02:00
sh4
sparc target/sparc: Switch to do_transaction_failed() hook 2019-09-17 12:01:00 +01:00
tilegx tcg: TCGMemOp is now accelerator independent MemOp 2019-09-03 08:30:38 -07:00
tricore tcg: TCGMemOp is now accelerator independent MemOp 2019-09-03 08:30:38 -07:00
unicore32
xtensa target/xtensa: regenerate and re-import test_mmuhifi_c3 core 2019-10-18 19:54:27 -07:00